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author | guoyin.chen <guoyin.chen@freescale.com> | 2013-08-16 10:34:29 +0800 |
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committer | guoyin.chen <guoyin.chen@freescale.com> | 2013-08-16 10:34:29 +0800 |
commit | 08967e3cf25b32dae50ca5455cd862ec86b06586 (patch) | |
tree | 388b22742fd868f1128931b3ec0c80cd782c0351 /arch | |
parent | 7faf590b972d9ca8d65183fb61a87566abfc7a45 (diff) | |
parent | bdde708ebfde4a8c1d3829578d3f6481a343533a (diff) |
Merge remote-tracking branch 'fsl-linux-sdk/imx_3.0.35_4.1.0' into imx_3.0.35_android
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-mx6/mm.c | 18 |
1 files changed, 15 insertions, 3 deletions
diff --git a/arch/arm/mach-mx6/mm.c b/arch/arm/mach-mx6/mm.c index 3cf6b226fca6..8d2c715f336b 100644 --- a/arch/arm/mach-mx6/mm.c +++ b/arch/arm/mach-mx6/mm.c @@ -111,9 +111,21 @@ int mxc_init_l2x0(void) writel(0x132, IO_ADDRESS(L2_BASE_ADDR + L2X0_TAG_LATENCY_CTRL)); writel(0x132, IO_ADDRESS(L2_BASE_ADDR + L2X0_DATA_LATENCY_CTRL)); - val = readl(IO_ADDRESS(L2_BASE_ADDR + L2X0_PREFETCH_CTRL)); - val |= 0x40800000; - writel(val, IO_ADDRESS(L2_BASE_ADDR + L2X0_PREFETCH_CTRL)); + /* + * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0 + * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2 + * But according to ARM PL310 errata: 752271 + * ID: 752271: Double linefill feature can cause data corruption + * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2 + * Workaround: The only workaround to this erratum is to disable the + * double linefill feature. This is the default behavior. + */ + if (!cpu_is_mx6q()) { + val = readl(IO_ADDRESS(L2_BASE_ADDR + L2X0_PREFETCH_CTRL)); + val |= 0x40800000; + writel(val, IO_ADDRESS(L2_BASE_ADDR + L2X0_PREFETCH_CTRL)); + } + val = readl(IO_ADDRESS(L2_BASE_ADDR + L2X0_POWER_CTRL)); val |= L2X0_DYNAMIC_CLK_GATING_EN; val |= L2X0_STNDBY_MODE_EN; |