diff options
| author | Bai Ping <b51503@freescale.com> | 2015-06-19 01:33:04 +0800 |
|---|---|---|
| committer | Bai Ping <b51503@freescale.com> | 2015-07-22 18:24:13 +0800 |
| commit | 00177b76f6db2859391310159d3f57f2d91a8057 (patch) | |
| tree | b57098b8afdc614f2fc09b7c80d09df0711cc078 /arch | |
| parent | 38309c03a70db895f2adb6a058ca4c48ccc3b2d7 (diff) | |
MLK-11117-02 ARM: imx6: update the clk switch code on imx6ul
Due to the clk tree info for AXI/AHB updating on i.MX6UL, the
busfreq enter/exit on i.MX6UL also need to be updated to align
to these changes. The AXI/AHB should be source from pll2_bus, and
the AHB clock divider value need to be set to 4 to make sure when
exiting from low bus mode, the AHB clock is also the original rate.
Signed-off-by: Bai Ping <b51503@freescale.com>
(cherry picked from commit e19096fae5c9c692d8bb560db10771dee34b3c10)
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-imx/busfreq-imx.c | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/arch/arm/mach-imx/busfreq-imx.c b/arch/arm/mach-imx/busfreq-imx.c index 5009267d8122..2408e4d3ab16 100644 --- a/arch/arm/mach-imx/busfreq-imx.c +++ b/arch/arm/mach-imx/busfreq-imx.c @@ -268,12 +268,19 @@ static void exit_lpm_imx6_up(void) * lower ahb/ocram's freq first to avoid too high * freq during parent switch from OSC to pll3. */ - imx_clk_set_rate(ahb_clk, LPAPM_CLK / 3); + if (cpu_is_imx6ul()) + imx_clk_set_rate(ahb_clk, LPAPM_CLK / 4); + else + imx_clk_set_rate(ahb_clk, LPAPM_CLK / 3); imx_clk_set_rate(ocram_clk, LPAPM_CLK / 2); /* set periph_clk2 to pll3 */ imx_clk_set_parent(periph_clk2_sel, pll3); + /* set periph clk to from pll2_bus on i.MX6UL */ + if (cpu_is_imx6ul()) + imx_clk_set_parent(periph_pre_clk, pll2_bus); /* set periph clk to from pll2_400 */ - imx_clk_set_parent(periph_pre_clk, pll2_400); + else + imx_clk_set_parent(periph_pre_clk, pll2_400); imx_clk_set_parent(periph_clk, periph_pre_clk); if (ddr_type == MMDC_MDMISC_DDR_TYPE_DDR3) |