diff options
| author | Bai Ping <b51503@freescale.com> | 2015-06-17 21:15:05 +0800 |
|---|---|---|
| committer | Bai Ping <b51503@freescale.com> | 2015-07-22 18:24:13 +0800 |
| commit | 38309c03a70db895f2adb6a058ca4c48ccc3b2d7 (patch) | |
| tree | c860873cc20c5fc675f2f3816158669d5573e39e /arch | |
| parent | 63ebf415bb3eda142468d1cf2e7d2b9bcca60e57 (diff) | |
MLK-11117-01 ARM: clk: imx6: adjust axi clock to 264MHz on imx6ul
According to the latest reference manual, the default AXI clock rate
should be 264MHz. Soucre AXI/AHB from pll2_bus to get the required
clock rate.
Signed-off-by: Bai Ping <b51503@freescale.com>
(cherry picked from commit 8221b17e0adb10f780f0fcf7d683148caa129eca)
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-imx/clk-imx6ul.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/clk-imx6ul.c b/arch/arm/mach-imx/clk-imx6ul.c index b9498d312f65..52b2962616f5 100644 --- a/arch/arm/mach-imx/clk-imx6ul.c +++ b/arch/arm/mach-imx/clk-imx6ul.c @@ -440,6 +440,16 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) imx_clk_set_parent(clks[IMX6UL_CLK_ENFC_SEL], clks[IMX6UL_CLK_PLL2_PFD2]); + /* Lower the AHB clock rate before changing the clock source. */ + imx_clk_set_rate(clks[IMX6UL_CLK_AHB], 99000000); + + /* Change periph_pre clock to pll2_bus to adjust AXI rate to 264MHz */ + imx_clk_set_parent(clks[IMX6UL_CLK_PERIPH_CLK2_SEL], clks[IMX6UL_CLK_PLL3_USB_OTG]); + imx_clk_set_parent(clks[IMX6UL_CLK_PERIPH], clks[IMX6UL_CLK_PERIPH_CLK2]); + imx_clk_set_parent(clks[IMX6UL_CLK_PERIPH_PRE], clks[IMX6UL_CLK_PLL2_BUS]); + imx_clk_set_parent(clks[IMX6UL_CLK_PERIPH], clks[IMX6UL_CLK_PERIPH_PRE]); + + imx_clk_set_rate(clks[IMX6UL_CLK_AHB], 132000000); /* Set initial power mode */ imx6q_set_lpm(WAIT_CLOCKED); |