tegra RM: Explicitly set core voltage on LP1 entry.

Explicitly set core voltage when DVFS is suspended to avoid LP1 entry
at high voltage caused by "last minute" system activity.

Change-Id: Iefa6ac3c0c76482871c9cd10d993c03a6a6c00c3
Reviewed-on: http://git-master/r/718
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>

2 files changed, 26 insertions, 2 deletions

diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_pmu_private.h b/arch/arm/mach-tegra/nvrm/core/common/nvrm_pmu_private.h
index 441344fab5ca..79c818d21838 100644
--- a/arch/arm/mach-tegra/nvrm/core/common/nvrm_pmu_private.h
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_pmu_private.h
@@ -41,8 +41,8 @@ extern "C"
 #endif  /* __cplusplus */
 
 // CPU rail lowering voltage delay (applicable only to the platforms
-// with dedicated CPU rail, and PMU default core voltage above nominal)
-#define NVRM_CPU_TO_CORE_DOWN_US (10000)
+// with dedicated CPU rail)
+#define NVRM_CPU_TO_CORE_DOWN_US (2000)
 
 // Default voltage returned in environment with no PMU support
 #define NVRM_NO_PMU_DEFAULT_VOLTAGE (1)
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_power_dfs.c b/arch/arm/mach-tegra/nvrm/core/common/nvrm_power_dfs.c
index f031ec95d592..fa1f110f236c 100644
--- a/arch/arm/mach-tegra/nvrm/core/common/nvrm_power_dfs.c
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_power_dfs.c
@@ -2554,6 +2554,7 @@ static void NvRmPrivDvsStopAtNominal(void)
 static void NvRmPrivDvsRun(void)
 {
     NvRmDvs* pDvs = &s_Dfs.VoltageScaler;
+    pDvs->UpdateFlag = NV_TRUE;
     pDvs->StopFlag = NV_FALSE;
 }
 
@@ -2617,6 +2618,29 @@ void NvRmPrivDfsSuspend(NvOdmSocPowerState state)
             }
             DfsKHz = pDfs->SuspendKHz;
         }
+
+        if (NvRmPrivIsCpuRailDedicated(pDfs->hRm))
+        {
+            NvRmDvs* pDvs = &s_Dfs.VoltageScaler;
+            NvRmMilliVolts v = NV_MAX(pDvs->DvsCorner.SystemMv,
+                                      NV_MAX(pDvs->DvsCorner.EmcMv,
+                                             pDvs->DvsCorner.ModulesMv));
+
+            // If CPU rail returns to default level by PMU underneath DVFS
+            // need to synchronize voltage after LP1 same way as after LP2
+            if (pDvs->VCpuOTPOnWakeup)
+                pDfs->VoltageScaler.Lp2SyncOTPFlag = NV_TRUE;
+
+            // If core voltage change was deferred until CPU voltage is
+            // settled - do it now
+            if (v < pDvs->CurrentCoreMv)
+            {
+                NvOsWaitUS(NVRM_CPU_TO_CORE_DOWN_US);
+                DvsChangeCoreVoltage(pDfs->hRm, pDvs, v);
+            }
+            NvOsDebugPrintf("DVFS set core at %dmV\n", pDvs->CurrentCoreMv);
+        }
+
         pDfs->VoltageScaler.StopFlag = NV_TRUE;
     }
     NvRmPrivUnlockSharedPll();