diff options
| author | Prashant Gaikwad <pgaikwad@nvidia.com> | 2012-01-03 15:48:45 +0530 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2012-01-06 17:05:11 +0530 |
| commit | 1e60bd6ec86b65ba77c43cfa133c651b13b22caa (patch) | |
| tree | d71365db8f447985b52fea6ae1e41bed24e7477c /arch | |
| parent | 5c44a3f0e7e7fc3b00c6d58921b322174b328152 (diff) | |
ARM: tegra: power: L2 cache sync only for CPU0 LP2
Bug 922010
Change-Id: I19724ae5d8421b2fccfc604ecb0a867d20fddf75
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/72986
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-tegra/sleep-t2.S | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/sleep-t2.S b/arch/arm/mach-tegra/sleep-t2.S index 01791439426b..f70360628f34 100644 --- a/arch/arm/mach-tegra/sleep-t2.S +++ b/arch/arm/mach-tegra/sleep-t2.S @@ -258,6 +258,9 @@ ENTRY(tegra2_sleep_wfi) #endif #ifdef CONFIG_CACHE_L2X0 + cpu_id r2 + cmp r2, #0 + bne no_l2_sync /* Issue a PL310 cache sync operation */ dsb mov32 r2, TEGRA_PL310_VIRT @@ -265,6 +268,8 @@ ENTRY(tegra2_sleep_wfi) add r2, r2, r1 mov r1, #0 str r1, [r2] + +no_l2_sync: #endif pop_ctx_regs r0, r1 @ restore context registers |