diff options
| author | Marc Zyngier <marc.zyngier@arm.com> | 2018-02-01 11:07:37 +0000 |
|---|---|---|
| committer | Winnie Hsu <whsu@nvidia.com> | 2018-04-28 23:31:14 -0700 |
| commit | 36591cfe15177a919d780b25cce5dfb304afaaa0 (patch) | |
| tree | b2ac04d5d1e9ab5b08cda986e23172dde12c7f85 /arch | |
| parent | de3110548b04b6a0b58b4c9d4235552388539ee0 (diff) | |
arm: Invalidate icache on prefetch abort outside of user mapping on Cortex-A15
** Not yet queued for inclusion in mainline **
In order to prevent aliasing attacks on the branch predictor,
invalidate the icache on Cortex-A15, which has the side effect
of invalidating the BTB. This requires ACTLR[0] to be set to 1
(secure operation).
Change-Id: I4bb8e3ec05853d739bebd8fb3c61657e252808c0
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1698400
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Tested-by: Bibek Basu <bbasu@nvidia.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/include/asm/cp15.h | 1 | ||||
| -rw-r--r-- | arch/arm/mm/fault.c | 4 |
2 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/include/asm/cp15.h b/arch/arm/include/asm/cp15.h index 43eddecc837d..d820fc5f043a 100644 --- a/arch/arm/include/asm/cp15.h +++ b/arch/arm/include/asm/cp15.h @@ -66,6 +66,7 @@ #define BPIALL __ACCESS_CP15(c7, 0, c5, 6) +#define ICIALLU __ACCESS_CP15(c7, 0, c5, 0) extern unsigned long cr_no_alignment; /* defined in entry-armv.S */ extern unsigned long cr_alignment; /* defined in entry-armv.S */ diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c index f18f94006fea..e8f42821a206 100644 --- a/arch/arm/mm/fault.c +++ b/arch/arm/mm/fault.c @@ -26,6 +26,7 @@ #include <asm/system_misc.h> #include <asm/system_info.h> #include <asm/tlbflush.h> +#include <asm/cputype.h> #include "fault.h" @@ -401,6 +402,9 @@ do_pabt_page_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs) #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR if (addr > TASK_SIZE) { switch (read_cpuid_part_number()) { + case ARM_CPU_PART_CORTEX_A15: + write_sysreg(0, ICIALLU); + break; } } #endif |