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authorScottPeterson <speterson@nvidia.com>2011-12-28 13:40:20 -0800
committerVarun Wadekar <vwadekar@nvidia.com>2012-01-06 17:08:38 +0530
commitfde0dd459ac5048614a4f4bf4cf86224480c846d (patch)
treedfceca21b0a8f1a892bc27881d5f529f9e27270c /arch
parent494a7b66ad5fc814b1344dd105d9f2dfad20a191 (diff)
arm: tegra: Disable pll_p_out clocks by default
Disable unused pll_p_out clocks until they are needed to reduce power. Change-Id: I60c2a7ca50a957f23ca20ec559dbbb1aa26ca797 Reviewed-on: http://git-master/r/72464 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-tegra/common.c12
-rw-r--r--arch/arm/mach-tegra/tegra3_clocks.c6
2 files changed, 9 insertions, 9 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index dd281d8d4f69..103634a9cec4 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -149,24 +149,24 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
{ "3d", "pll_c", 0, false },
#else
{ "pll_p", NULL, 408000000, true },
- { "pll_p_out1", "pll_p", 9600000, true },
- { "pll_p_out2", "pll_p", 48000000, true },
+ { "pll_p_out1", "pll_p", 9600000, false },
+ { "pll_p_out2", "pll_p", 48000000, false },
{ "pll_p_out3", "pll_p", 102000000, true },
{ "pll_m_out1", "pll_m", 275000000, false },
- { "pll_p_out4", "pll_p", 102000000, true },
+ { "pll_p_out4", "pll_p", 102000000, false },
{ "sclk", "pll_p_out4", 102000000, true },
{ "hclk", "sclk", 102000000, true },
{ "pclk", "hclk", 51000000, true },
#endif
#else
{ "pll_p", NULL, 216000000, true },
- { "pll_p_out1", "pll_p", 28800000, true },
- { "pll_p_out2", "pll_p", 48000000, true },
+ { "pll_p_out1", "pll_p", 28800000, false },
+ { "pll_p_out2", "pll_p", 48000000, false },
{ "pll_p_out3", "pll_p", 72000000, true },
{ "pll_m_out1", "pll_m", 275000000, true },
{ "pll_c", NULL, ULONG_MAX, false },
{ "pll_c_out1", "pll_c", 208000000, false },
- { "pll_p_out4", "pll_p", 108000000, true },
+ { "pll_p_out4", "pll_p", 108000000, false },
{ "sclk", "pll_p_out4", 108000000, true },
{ "hclk", "sclk", 108000000, true },
{ "pclk", "hclk", 54000000, true },
diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c
index 0ce0dcde941e..e0b0c7389385 100644
--- a/arch/arm/mach-tegra/tegra3_clocks.c
+++ b/arch/arm/mach-tegra/tegra3_clocks.c
@@ -3178,7 +3178,7 @@ static struct clk tegra_pll_p = {
static struct clk tegra_pll_p_out1 = {
.name = "pll_p_out1",
.ops = &tegra_pll_div_ops,
- .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
+ .flags = DIV_U71 | DIV_U71_FIXED,
.parent = &tegra_pll_p,
.reg = 0xa4,
.reg_shift = 0,
@@ -3188,7 +3188,7 @@ static struct clk tegra_pll_p_out1 = {
static struct clk tegra_pll_p_out2 = {
.name = "pll_p_out2",
.ops = &tegra_pll_div_ops,
- .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
+ .flags = DIV_U71 | DIV_U71_FIXED,
.parent = &tegra_pll_p,
.reg = 0xa4,
.reg_shift = 16,
@@ -3198,7 +3198,7 @@ static struct clk tegra_pll_p_out2 = {
static struct clk tegra_pll_p_out3 = {
.name = "pll_p_out3",
.ops = &tegra_pll_div_ops,
- .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
+ .flags = DIV_U71 | DIV_U71_FIXED,
.parent = &tegra_pll_p,
.reg = 0xa8,
.reg_shift = 0,