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authorSang-Hun Lee <sanlee@nvidia.com>2013-04-29 10:59:26 -0700
committerRiham Haidar <rhaidar@nvidia.com>2013-04-30 12:24:23 -0700
commitaa528008d1fc4f706e897f7618d59f8e577129a0 (patch)
treec0570087e30bce0242de72bde5dab97b9a4e0610 /arch
parent0c9ee6cba429689be54f5e8ae370ea9dfed4ab75 (diff)
ARM: Tegra: Roth: Update DVFS for P2560
Bug 1181038 Change-Id: I1bb349448106dcc30e7d7fd6d62bbe9dfd2f9f7f Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com> Reviewed-on: http://git-master/r/223940 Reviewed-by: Matt Wagner <mwagner@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-tegra/board-roth-memory.c1030
1 files changed, 515 insertions, 515 deletions
diff --git a/arch/arm/mach-tegra/board-roth-memory.c b/arch/arm/mach-tegra/board-roth-memory.c
index f2f78ec85b72..8667b356a924 100644
--- a/arch/arm/mach-tegra/board-roth-memory.c
+++ b/arch/arm/mach-tegra/board-roth-memory.c
@@ -2607,11 +2607,11 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000000, /* EMC_WEXT */
0x00000005, /* EMC_WDV */
0x0000000f, /* EMC_WDV_MASK */
- 0x00000005, /* EMC_IBDLY */
+ 0x00000006, /* EMC_IBDLY */
0x00010000, /* EMC_PUTERM_EXTRA */
0x00000000, /* EMC_CDB_CNTL_2 */
0x00000004, /* EMC_QRST */
- 0x0000000e, /* EMC_RDV_MASK */
+ 0x0000000f, /* EMC_RDV_MASK */
0x00000060, /* EMC_REFRESH */
0x00000000, /* EMC_BURST_REFRESH_NUM */
0x00000018, /* EMC_PRE_REFRESH_REQ_CNT */
@@ -2637,10 +2637,10 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x0000aa88, /* EMC_FBIO_CFG5 */
0x002c00a0, /* EMC_CFG_DIG_DLL */
0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
- 0x00070000, /* EMC_DLL_XFORM_DQS4 */
- 0x00070000, /* EMC_DLL_XFORM_DQS5 */
- 0x00070000, /* EMC_DLL_XFORM_DQS6 */
- 0x00070000, /* EMC_DLL_XFORM_DQS7 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS4 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS5 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS6 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS7 */
0x00000000, /* EMC_DLL_XFORM_QUSE4 */
0x00000000, /* EMC_DLL_XFORM_QUSE5 */
0x00000000, /* EMC_DLL_XFORM_QUSE6 */
@@ -2655,10 +2655,10 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000000, /* EMC_XM2DQPADCTRL2 */
0x77ffc085, /* EMC_XM2CLKPADCTRL */
0x81f1f108, /* EMC_XM2COMPPADCTRL */
- 0x03035504, /* EMC_XM2VTTGENPADCTRL */
+ 0x03037504, /* EMC_XM2VTTGENPADCTRL */
0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
0x0000003f, /* EMC_DSR_VTTGEN_DRV */
- 0x00000000, /* EMC_TXDSRVTTGEN */
+ 0x00000007, /* EMC_TXDSRVTTGEN */
0x02000000, /* EMC_FBIO_SPARE */
0x00000802, /* EMC_CTT_TERM_CTRL */
0x00000000, /* EMC_ZCAL_INTERVAL */
@@ -2693,29 +2693,29 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
},
{
0x00000000, /* EMC_CDB_CNTL_1 */
- 0x00000004, /* EMC_FBIO_CFG6 */
+ 0x00000006, /* EMC_FBIO_CFG6 */
0x00000006, /* EMC_QUSE */
- 0x00000003, /* EMC_EINPUT */
+ 0x00000004, /* EMC_EINPUT */
0x00000004, /* EMC_EINPUT_DURATION */
- 0x00070000, /* EMC_DLL_XFORM_DQS0 */
- 0x0000000a, /* EMC_QSAFE */
+ 0x00078000, /* EMC_DLL_XFORM_DQS0 */
+ 0x00000009, /* EMC_QSAFE */
0x00000000, /* EMC_DLL_XFORM_QUSE0 */
- 0x0000000c, /* EMC_RDV */
+ 0x0000000d, /* EMC_RDV */
0x00249249, /* EMC_XM2DQSPADCTRL4 */
0x20820800, /* EMC_XM2DQSPADCTRL3 */
- 0x00070000, /* EMC_DLL_XFORM_DQ0 */
- 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+ 0x00078000, /* EMC_DLL_XFORM_DQ0 */
+ 0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
0x00000000, /* EMC_DLL_XFORM_ADDR0 */
0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
0x00000000, /* EMC_DLL_XFORM_ADDR1 */
0x00000000, /* EMC_DLL_XFORM_ADDR2 */
- 0x00070000, /* EMC_DLL_XFORM_DQS1 */
- 0x00070000, /* EMC_DLL_XFORM_DQS2 */
- 0x00070000, /* EMC_DLL_XFORM_DQS3 */
- 0x00070000, /* EMC_DLL_XFORM_DQ1 */
- 0x00070000, /* EMC_DLL_XFORM_DQ2 */
- 0x00070000, /* EMC_DLL_XFORM_DQ3 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS1 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS2 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS3 */
+ 0x00078000, /* EMC_DLL_XFORM_DQ1 */
+ 0x00078000, /* EMC_DLL_XFORM_DQ2 */
+ 0x00078000, /* EMC_DLL_XFORM_DQ3 */
0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
@@ -2725,29 +2725,29 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
},
{
0x00000000, /* EMC_CDB_CNTL_1 */
- 0x00000004, /* EMC_FBIO_CFG6 */
+ 0x00000006, /* EMC_FBIO_CFG6 */
0x00000006, /* EMC_QUSE */
- 0x00000003, /* EMC_EINPUT */
+ 0x00000004, /* EMC_EINPUT */
0x00000004, /* EMC_EINPUT_DURATION */
- 0x00070000, /* EMC_DLL_XFORM_DQS0 */
- 0x0000000a, /* EMC_QSAFE */
+ 0x00078000, /* EMC_DLL_XFORM_DQS0 */
+ 0x00000009, /* EMC_QSAFE */
0x00000000, /* EMC_DLL_XFORM_QUSE0 */
- 0x0000000c, /* EMC_RDV */
+ 0x0000000d, /* EMC_RDV */
0x00249249, /* EMC_XM2DQSPADCTRL4 */
0x20820800, /* EMC_XM2DQSPADCTRL3 */
- 0x00070000, /* EMC_DLL_XFORM_DQ0 */
- 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+ 0x00078000, /* EMC_DLL_XFORM_DQ0 */
+ 0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
0x00000000, /* EMC_DLL_XFORM_ADDR0 */
0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
0x00000000, /* EMC_DLL_XFORM_ADDR1 */
0x00000000, /* EMC_DLL_XFORM_ADDR2 */
- 0x00070000, /* EMC_DLL_XFORM_DQS1 */
- 0x00070000, /* EMC_DLL_XFORM_DQS2 */
- 0x00070000, /* EMC_DLL_XFORM_DQS3 */
- 0x00070000, /* EMC_DLL_XFORM_DQ1 */
- 0x00070000, /* EMC_DLL_XFORM_DQ2 */
- 0x00070000, /* EMC_DLL_XFORM_DQ3 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS1 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS2 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS3 */
+ 0x00078000, /* EMC_DLL_XFORM_DQ1 */
+ 0x00078000, /* EMC_DLL_XFORM_DQ2 */
+ 0x00078000, /* EMC_DLL_XFORM_DQ3 */
0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
@@ -2770,7 +2770,7 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
},
0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
- 0x7320000e, /* EMC_CFG */
+ 0x7324000e, /* EMC_CFG */
0x80001221, /* Mode Register 0 */
0x80100003, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
@@ -2803,11 +2803,11 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000000, /* EMC_WEXT */
0x00000005, /* EMC_WDV */
0x0000000f, /* EMC_WDV_MASK */
- 0x00000005, /* EMC_IBDLY */
+ 0x00000006, /* EMC_IBDLY */
0x00010000, /* EMC_PUTERM_EXTRA */
0x00000000, /* EMC_CDB_CNTL_2 */
0x00000004, /* EMC_QRST */
- 0x0000000e, /* EMC_RDV_MASK */
+ 0x0000000f, /* EMC_RDV_MASK */
0x0000009a, /* EMC_REFRESH */
0x00000000, /* EMC_BURST_REFRESH_NUM */
0x00000026, /* EMC_PRE_REFRESH_REQ_CNT */
@@ -2833,10 +2833,10 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x0000aa88, /* EMC_FBIO_CFG5 */
0x002c00a0, /* EMC_CFG_DIG_DLL */
0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
- 0x00070000, /* EMC_DLL_XFORM_DQS4 */
- 0x00070000, /* EMC_DLL_XFORM_DQS5 */
- 0x00070000, /* EMC_DLL_XFORM_DQS6 */
- 0x00070000, /* EMC_DLL_XFORM_DQS7 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS4 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS5 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS6 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS7 */
0x00000000, /* EMC_DLL_XFORM_QUSE4 */
0x00000000, /* EMC_DLL_XFORM_QUSE5 */
0x00000000, /* EMC_DLL_XFORM_QUSE6 */
@@ -2851,10 +2851,10 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000000, /* EMC_XM2DQPADCTRL2 */
0x77ffc085, /* EMC_XM2CLKPADCTRL */
0x81f1f108, /* EMC_XM2COMPPADCTRL */
- 0x03035504, /* EMC_XM2VTTGENPADCTRL */
+ 0x03037504, /* EMC_XM2VTTGENPADCTRL */
0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
0x0000003f, /* EMC_DSR_VTTGEN_DRV */
- 0x00000000, /* EMC_TXDSRVTTGEN */
+ 0x0000000b, /* EMC_TXDSRVTTGEN */
0x02000000, /* EMC_FBIO_SPARE */
0x00000802, /* EMC_CTT_TERM_CTRL */
0x00000000, /* EMC_ZCAL_INTERVAL */
@@ -2889,29 +2889,29 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
},
{
0x00000000, /* EMC_CDB_CNTL_1 */
- 0x00000004, /* EMC_FBIO_CFG6 */
+ 0x00000006, /* EMC_FBIO_CFG6 */
0x00000006, /* EMC_QUSE */
- 0x00000003, /* EMC_EINPUT */
+ 0x00000004, /* EMC_EINPUT */
0x00000004, /* EMC_EINPUT_DURATION */
- 0x00070000, /* EMC_DLL_XFORM_DQS0 */
- 0x0000000a, /* EMC_QSAFE */
+ 0x00078000, /* EMC_DLL_XFORM_DQS0 */
+ 0x00000009, /* EMC_QSAFE */
0x00000000, /* EMC_DLL_XFORM_QUSE0 */
- 0x0000000c, /* EMC_RDV */
+ 0x0000000d, /* EMC_RDV */
0x00249249, /* EMC_XM2DQSPADCTRL4 */
0x20820800, /* EMC_XM2DQSPADCTRL3 */
- 0x00070000, /* EMC_DLL_XFORM_DQ0 */
- 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+ 0x00078000, /* EMC_DLL_XFORM_DQ0 */
+ 0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
0x00000000, /* EMC_DLL_XFORM_ADDR0 */
0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
0x00000000, /* EMC_DLL_XFORM_ADDR1 */
0x00000000, /* EMC_DLL_XFORM_ADDR2 */
- 0x00070000, /* EMC_DLL_XFORM_DQS1 */
- 0x00070000, /* EMC_DLL_XFORM_DQS2 */
- 0x00070000, /* EMC_DLL_XFORM_DQS3 */
- 0x00070000, /* EMC_DLL_XFORM_DQ1 */
- 0x00070000, /* EMC_DLL_XFORM_DQ2 */
- 0x00070000, /* EMC_DLL_XFORM_DQ3 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS1 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS2 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS3 */
+ 0x00078000, /* EMC_DLL_XFORM_DQ1 */
+ 0x00078000, /* EMC_DLL_XFORM_DQ2 */
+ 0x00078000, /* EMC_DLL_XFORM_DQ3 */
0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
@@ -2921,29 +2921,29 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
},
{
0x00000000, /* EMC_CDB_CNTL_1 */
- 0x00000004, /* EMC_FBIO_CFG6 */
+ 0x00000006, /* EMC_FBIO_CFG6 */
0x00000006, /* EMC_QUSE */
- 0x00000003, /* EMC_EINPUT */
+ 0x00000004, /* EMC_EINPUT */
0x00000004, /* EMC_EINPUT_DURATION */
- 0x00070000, /* EMC_DLL_XFORM_DQS0 */
- 0x0000000a, /* EMC_QSAFE */
+ 0x00078000, /* EMC_DLL_XFORM_DQS0 */
+ 0x00000009, /* EMC_QSAFE */
0x00000000, /* EMC_DLL_XFORM_QUSE0 */
- 0x0000000c, /* EMC_RDV */
+ 0x0000000d, /* EMC_RDV */
0x00249249, /* EMC_XM2DQSPADCTRL4 */
0x20820800, /* EMC_XM2DQSPADCTRL3 */
- 0x00070000, /* EMC_DLL_XFORM_DQ0 */
- 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+ 0x00078000, /* EMC_DLL_XFORM_DQ0 */
+ 0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
0x00000000, /* EMC_DLL_XFORM_ADDR0 */
0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
0x00000000, /* EMC_DLL_XFORM_ADDR1 */
0x00000000, /* EMC_DLL_XFORM_ADDR2 */
- 0x00070000, /* EMC_DLL_XFORM_DQS1 */
- 0x00070000, /* EMC_DLL_XFORM_DQS2 */
- 0x00070000, /* EMC_DLL_XFORM_DQS3 */
- 0x00070000, /* EMC_DLL_XFORM_DQ1 */
- 0x00070000, /* EMC_DLL_XFORM_DQ2 */
- 0x00070000, /* EMC_DLL_XFORM_DQ3 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS1 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS2 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS3 */
+ 0x00078000, /* EMC_DLL_XFORM_DQ1 */
+ 0x00078000, /* EMC_DLL_XFORM_DQ2 */
+ 0x00078000, /* EMC_DLL_XFORM_DQ3 */
0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
@@ -2966,7 +2966,7 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
},
0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
- 0x7320000e, /* EMC_CFG */
+ 0x7324000e, /* EMC_CFG */
0x80001221, /* Mode Register 0 */
0x80100003, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
@@ -2999,11 +2999,11 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000000, /* EMC_WEXT */
0x00000005, /* EMC_WDV */
0x0000000f, /* EMC_WDV_MASK */
- 0x00000005, /* EMC_IBDLY */
+ 0x00000006, /* EMC_IBDLY */
0x00010000, /* EMC_PUTERM_EXTRA */
0x00000000, /* EMC_CDB_CNTL_2 */
0x00000004, /* EMC_QRST */
- 0x0000000e, /* EMC_RDV_MASK */
+ 0x0000000f, /* EMC_RDV_MASK */
0x00000134, /* EMC_REFRESH */
0x00000000, /* EMC_BURST_REFRESH_NUM */
0x0000004d, /* EMC_PRE_REFRESH_REQ_CNT */
@@ -3029,10 +3029,10 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x0000aa88, /* EMC_FBIO_CFG5 */
0x002c00a0, /* EMC_CFG_DIG_DLL */
0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
- 0x00070000, /* EMC_DLL_XFORM_DQS4 */
- 0x00070000, /* EMC_DLL_XFORM_DQS5 */
- 0x00070000, /* EMC_DLL_XFORM_DQS6 */
- 0x00070000, /* EMC_DLL_XFORM_DQS7 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS4 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS5 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS6 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS7 */
0x00000000, /* EMC_DLL_XFORM_QUSE4 */
0x00000000, /* EMC_DLL_XFORM_QUSE5 */
0x00000000, /* EMC_DLL_XFORM_QUSE6 */
@@ -3047,10 +3047,10 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000000, /* EMC_XM2DQPADCTRL2 */
0x77ffc085, /* EMC_XM2CLKPADCTRL */
0x81f1f108, /* EMC_XM2COMPPADCTRL */
- 0x03035504, /* EMC_XM2VTTGENPADCTRL */
+ 0x03037504, /* EMC_XM2VTTGENPADCTRL */
0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
0x0000003f, /* EMC_DSR_VTTGEN_DRV */
- 0x00000000, /* EMC_TXDSRVTTGEN */
+ 0x00000015, /* EMC_TXDSRVTTGEN */
0x02000000, /* EMC_FBIO_SPARE */
0x00000802, /* EMC_CTT_TERM_CTRL */
0x00000000, /* EMC_ZCAL_INTERVAL */
@@ -3085,29 +3085,29 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
},
{
0x00000000, /* EMC_CDB_CNTL_1 */
- 0x00000004, /* EMC_FBIO_CFG6 */
+ 0x00000006, /* EMC_FBIO_CFG6 */
0x00000006, /* EMC_QUSE */
- 0x00000003, /* EMC_EINPUT */
+ 0x00000004, /* EMC_EINPUT */
0x00000004, /* EMC_EINPUT_DURATION */
- 0x00070000, /* EMC_DLL_XFORM_DQS0 */
- 0x0000000a, /* EMC_QSAFE */
+ 0x00078000, /* EMC_DLL_XFORM_DQS0 */
+ 0x00000009, /* EMC_QSAFE */
0x00000000, /* EMC_DLL_XFORM_QUSE0 */
- 0x0000000c, /* EMC_RDV */
+ 0x0000000d, /* EMC_RDV */
0x00249249, /* EMC_XM2DQSPADCTRL4 */
0x20820800, /* EMC_XM2DQSPADCTRL3 */
- 0x00070000, /* EMC_DLL_XFORM_DQ0 */
- 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+ 0x00078000, /* EMC_DLL_XFORM_DQ0 */
+ 0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
0x00000000, /* EMC_DLL_XFORM_ADDR0 */
0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
0x00000000, /* EMC_DLL_XFORM_ADDR1 */
0x00000000, /* EMC_DLL_XFORM_ADDR2 */
- 0x00070000, /* EMC_DLL_XFORM_DQS1 */
- 0x00070000, /* EMC_DLL_XFORM_DQS2 */
- 0x00070000, /* EMC_DLL_XFORM_DQS3 */
- 0x00070000, /* EMC_DLL_XFORM_DQ1 */
- 0x00070000, /* EMC_DLL_XFORM_DQ2 */
- 0x00070000, /* EMC_DLL_XFORM_DQ3 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS1 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS2 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS3 */
+ 0x00078000, /* EMC_DLL_XFORM_DQ1 */
+ 0x00078000, /* EMC_DLL_XFORM_DQ2 */
+ 0x00078000, /* EMC_DLL_XFORM_DQ3 */
0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
@@ -3117,29 +3117,29 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
},
{
0x00000000, /* EMC_CDB_CNTL_1 */
- 0x00000004, /* EMC_FBIO_CFG6 */
+ 0x00000006, /* EMC_FBIO_CFG6 */
0x00000006, /* EMC_QUSE */
- 0x00000003, /* EMC_EINPUT */
+ 0x00000004, /* EMC_EINPUT */
0x00000004, /* EMC_EINPUT_DURATION */
- 0x00070000, /* EMC_DLL_XFORM_DQS0 */
- 0x0000000a, /* EMC_QSAFE */
+ 0x00078000, /* EMC_DLL_XFORM_DQS0 */
+ 0x00000009, /* EMC_QSAFE */
0x00000000, /* EMC_DLL_XFORM_QUSE0 */
- 0x0000000c, /* EMC_RDV */
+ 0x0000000d, /* EMC_RDV */
0x00249249, /* EMC_XM2DQSPADCTRL4 */
0x20820800, /* EMC_XM2DQSPADCTRL3 */
- 0x00070000, /* EMC_DLL_XFORM_DQ0 */
- 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+ 0x00078000, /* EMC_DLL_XFORM_DQ0 */
+ 0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
0x00000000, /* EMC_DLL_XFORM_ADDR0 */
0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
0x00000000, /* EMC_DLL_XFORM_ADDR1 */
0x00000000, /* EMC_DLL_XFORM_ADDR2 */
- 0x00070000, /* EMC_DLL_XFORM_DQS1 */
- 0x00070000, /* EMC_DLL_XFORM_DQS2 */
- 0x00070000, /* EMC_DLL_XFORM_DQS3 */
- 0x00070000, /* EMC_DLL_XFORM_DQ1 */
- 0x00070000, /* EMC_DLL_XFORM_DQ2 */
- 0x00070000, /* EMC_DLL_XFORM_DQ3 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS1 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS2 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS3 */
+ 0x00078000, /* EMC_DLL_XFORM_DQ1 */
+ 0x00078000, /* EMC_DLL_XFORM_DQ2 */
+ 0x00078000, /* EMC_DLL_XFORM_DQ3 */
0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
@@ -3162,7 +3162,7 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
},
0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
- 0x7320000e, /* EMC_CFG */
+ 0x7324000e, /* EMC_CFG */
0x80001221, /* Mode Register 0 */
0x80100003, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
@@ -3195,11 +3195,11 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000000, /* EMC_WEXT */
0x00000005, /* EMC_WDV */
0x0000000f, /* EMC_WDV_MASK */
- 0x00000005, /* EMC_IBDLY */
+ 0x00000006, /* EMC_IBDLY */
0x00010000, /* EMC_PUTERM_EXTRA */
0x00000000, /* EMC_CDB_CNTL_2 */
0x00000004, /* EMC_QRST */
- 0x0000000e, /* EMC_RDV_MASK */
+ 0x0000000f, /* EMC_RDV_MASK */
0x00000202, /* EMC_REFRESH */
0x00000000, /* EMC_BURST_REFRESH_NUM */
0x00000080, /* EMC_PRE_REFRESH_REQ_CNT */
@@ -3225,10 +3225,10 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x0000aa88, /* EMC_FBIO_CFG5 */
0x002c00a0, /* EMC_CFG_DIG_DLL */
0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
- 0x00070000, /* EMC_DLL_XFORM_DQS4 */
- 0x00070000, /* EMC_DLL_XFORM_DQS5 */
- 0x00070000, /* EMC_DLL_XFORM_DQS6 */
- 0x00070000, /* EMC_DLL_XFORM_DQS7 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS4 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS5 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS6 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS7 */
0x00000000, /* EMC_DLL_XFORM_QUSE4 */
0x00000000, /* EMC_DLL_XFORM_QUSE5 */
0x00000000, /* EMC_DLL_XFORM_QUSE6 */
@@ -3243,10 +3243,10 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000000, /* EMC_XM2DQPADCTRL2 */
0x77ffc085, /* EMC_XM2CLKPADCTRL */
0x81f1f108, /* EMC_XM2COMPPADCTRL */
- 0x03035504, /* EMC_XM2VTTGENPADCTRL */
+ 0x03037504, /* EMC_XM2VTTGENPADCTRL */
0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
0x0000003f, /* EMC_DSR_VTTGEN_DRV */
- 0x00000000, /* EMC_TXDSRVTTGEN */
+ 0x00000022, /* EMC_TXDSRVTTGEN */
0x02000000, /* EMC_FBIO_SPARE */
0x00000802, /* EMC_CTT_TERM_CTRL */
0x00000000, /* EMC_ZCAL_INTERVAL */
@@ -3257,7 +3257,7 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
0x00000000, /* EMC_CTT */
0x00000000, /* EMC_CTT_DURATION */
- 0x8000050d, /* EMC_DYN_SELF_REF_CONTROL */
+ 0x8000050e, /* EMC_DYN_SELF_REF_CONTROL */
0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
0x00000001, /* MC_EMEM_ARB_CFG */
@@ -3281,29 +3281,29 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
},
{
0x00000000, /* EMC_CDB_CNTL_1 */
- 0x00000004, /* EMC_FBIO_CFG6 */
+ 0x00000006, /* EMC_FBIO_CFG6 */
0x00000006, /* EMC_QUSE */
- 0x00000003, /* EMC_EINPUT */
+ 0x00000004, /* EMC_EINPUT */
0x00000004, /* EMC_EINPUT_DURATION */
- 0x00070000, /* EMC_DLL_XFORM_DQS0 */
- 0x0000000a, /* EMC_QSAFE */
+ 0x00078000, /* EMC_DLL_XFORM_DQS0 */
+ 0x00000009, /* EMC_QSAFE */
0x00000000, /* EMC_DLL_XFORM_QUSE0 */
- 0x0000000c, /* EMC_RDV */
+ 0x0000000d, /* EMC_RDV */
0x00249249, /* EMC_XM2DQSPADCTRL4 */
0x20820800, /* EMC_XM2DQSPADCTRL3 */
- 0x00070000, /* EMC_DLL_XFORM_DQ0 */
- 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+ 0x00078000, /* EMC_DLL_XFORM_DQ0 */
+ 0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
0x00000000, /* EMC_DLL_XFORM_ADDR0 */
- 0x00001e1e, /* EMC_XM2CLKPADCTRL2 */
+ 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
0x00000000, /* EMC_DLL_XFORM_ADDR1 */
0x00000000, /* EMC_DLL_XFORM_ADDR2 */
- 0x00070000, /* EMC_DLL_XFORM_DQS1 */
- 0x00070000, /* EMC_DLL_XFORM_DQS2 */
- 0x00070000, /* EMC_DLL_XFORM_DQS3 */
- 0x00070000, /* EMC_DLL_XFORM_DQ1 */
- 0x00070000, /* EMC_DLL_XFORM_DQ2 */
- 0x00070000, /* EMC_DLL_XFORM_DQ3 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS1 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS2 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS3 */
+ 0x00078000, /* EMC_DLL_XFORM_DQ1 */
+ 0x00078000, /* EMC_DLL_XFORM_DQ2 */
+ 0x00078000, /* EMC_DLL_XFORM_DQ3 */
0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
@@ -3313,29 +3313,29 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
},
{
0x00000000, /* EMC_CDB_CNTL_1 */
- 0x00000004, /* EMC_FBIO_CFG6 */
+ 0x00000006, /* EMC_FBIO_CFG6 */
0x00000006, /* EMC_QUSE */
- 0x00000003, /* EMC_EINPUT */
+ 0x00000004, /* EMC_EINPUT */
0x00000004, /* EMC_EINPUT_DURATION */
- 0x00070000, /* EMC_DLL_XFORM_DQS0 */
- 0x0000000a, /* EMC_QSAFE */
+ 0x00078000, /* EMC_DLL_XFORM_DQS0 */
+ 0x00000009, /* EMC_QSAFE */
0x00000000, /* EMC_DLL_XFORM_QUSE0 */
- 0x0000000c, /* EMC_RDV */
+ 0x0000000d, /* EMC_RDV */
0x00249249, /* EMC_XM2DQSPADCTRL4 */
0x20820800, /* EMC_XM2DQSPADCTRL3 */
- 0x00070000, /* EMC_DLL_XFORM_DQ0 */
- 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+ 0x00078000, /* EMC_DLL_XFORM_DQ0 */
+ 0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
0x00000000, /* EMC_DLL_XFORM_ADDR0 */
- 0x00001e1e, /* EMC_XM2CLKPADCTRL2 */
+ 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
0x00000000, /* EMC_DLL_XFORM_ADDR1 */
0x00000000, /* EMC_DLL_XFORM_ADDR2 */
- 0x00070000, /* EMC_DLL_XFORM_DQS1 */
- 0x00070000, /* EMC_DLL_XFORM_DQS2 */
- 0x00070000, /* EMC_DLL_XFORM_DQS3 */
- 0x00070000, /* EMC_DLL_XFORM_DQ1 */
- 0x00070000, /* EMC_DLL_XFORM_DQ2 */
- 0x00070000, /* EMC_DLL_XFORM_DQ3 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS1 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS2 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS3 */
+ 0x00078000, /* EMC_DLL_XFORM_DQ1 */
+ 0x00078000, /* EMC_DLL_XFORM_DQ2 */
+ 0x00078000, /* EMC_DLL_XFORM_DQ3 */
0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
@@ -3358,7 +3358,7 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
},
0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
- 0x7320000e, /* EMC_CFG */
+ 0x7324000e, /* EMC_CFG */
0x80001221, /* Mode Register 0 */
0x80100003, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
@@ -3391,11 +3391,11 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000000, /* EMC_WEXT */
0x00000005, /* EMC_WDV */
0x0000000f, /* EMC_WDV_MASK */
- 0x00000005, /* EMC_IBDLY */
+ 0x00000006, /* EMC_IBDLY */
0x00010000, /* EMC_PUTERM_EXTRA */
0x00000000, /* EMC_CDB_CNTL_2 */
0x00000004, /* EMC_QRST */
- 0x0000000e, /* EMC_RDV_MASK */
+ 0x0000000f, /* EMC_RDV_MASK */
0x00000303, /* EMC_REFRESH */
0x00000000, /* EMC_BURST_REFRESH_NUM */
0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */
@@ -3421,10 +3421,10 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x0000aa88, /* EMC_FBIO_CFG5 */
0x002c00a0, /* EMC_CFG_DIG_DLL */
0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
- 0x00070000, /* EMC_DLL_XFORM_DQS4 */
- 0x00070000, /* EMC_DLL_XFORM_DQS5 */
- 0x00070000, /* EMC_DLL_XFORM_DQS6 */
- 0x00070000, /* EMC_DLL_XFORM_DQS7 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS4 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS5 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS6 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS7 */
0x00000000, /* EMC_DLL_XFORM_QUSE4 */
0x00000000, /* EMC_DLL_XFORM_QUSE5 */
0x00000000, /* EMC_DLL_XFORM_QUSE6 */
@@ -3439,10 +3439,10 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000000, /* EMC_XM2DQPADCTRL2 */
0x77ffc085, /* EMC_XM2CLKPADCTRL */
0x81f1f108, /* EMC_XM2COMPPADCTRL */
- 0x03035504, /* EMC_XM2VTTGENPADCTRL */
+ 0x03037504, /* EMC_XM2VTTGENPADCTRL */
0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
0x0000003f, /* EMC_DSR_VTTGEN_DRV */
- 0x00000000, /* EMC_TXDSRVTTGEN */
+ 0x00000033, /* EMC_TXDSRVTTGEN */
0x02000000, /* EMC_FBIO_SPARE */
0x00000802, /* EMC_CTT_TERM_CTRL */
0x00000000, /* EMC_ZCAL_INTERVAL */
@@ -3453,7 +3453,7 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
0x00000000, /* EMC_CTT */
0x00000000, /* EMC_CTT_DURATION */
- 0x80000714, /* EMC_DYN_SELF_REF_CONTROL */
+ 0x80000713, /* EMC_DYN_SELF_REF_CONTROL */
0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
0x08000001, /* MC_EMEM_ARB_CFG */
@@ -3479,27 +3479,27 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000000, /* EMC_CDB_CNTL_1 */
0x00000006, /* EMC_FBIO_CFG6 */
0x00000006, /* EMC_QUSE */
- 0x00000005, /* EMC_EINPUT */
+ 0x00000004, /* EMC_EINPUT */
0x00000004, /* EMC_EINPUT_DURATION */
- 0x00070000, /* EMC_DLL_XFORM_DQS0 */
- 0x0000000a, /* EMC_QSAFE */
+ 0x00078000, /* EMC_DLL_XFORM_DQS0 */
+ 0x00000009, /* EMC_QSAFE */
0x00000000, /* EMC_DLL_XFORM_QUSE0 */
- 0x0000000c, /* EMC_RDV */
+ 0x0000000d, /* EMC_RDV */
0x00249249, /* EMC_XM2DQSPADCTRL4 */
0x20820800, /* EMC_XM2DQSPADCTRL3 */
- 0x00070000, /* EMC_DLL_XFORM_DQ0 */
- 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+ 0x00078000, /* EMC_DLL_XFORM_DQ0 */
+ 0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
0x00000000, /* EMC_DLL_XFORM_ADDR0 */
0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
0x00000000, /* EMC_DLL_XFORM_ADDR1 */
0x00000000, /* EMC_DLL_XFORM_ADDR2 */
- 0x00070000, /* EMC_DLL_XFORM_DQS1 */
- 0x00070000, /* EMC_DLL_XFORM_DQS2 */
- 0x00070000, /* EMC_DLL_XFORM_DQS3 */
- 0x00070000, /* EMC_DLL_XFORM_DQ1 */
- 0x00070000, /* EMC_DLL_XFORM_DQ2 */
- 0x00070000, /* EMC_DLL_XFORM_DQ3 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS1 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS2 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS3 */
+ 0x00078000, /* EMC_DLL_XFORM_DQ1 */
+ 0x00078000, /* EMC_DLL_XFORM_DQ2 */
+ 0x00078000, /* EMC_DLL_XFORM_DQ3 */
0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
@@ -3511,27 +3511,27 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000000, /* EMC_CDB_CNTL_1 */
0x00000006, /* EMC_FBIO_CFG6 */
0x00000006, /* EMC_QUSE */
- 0x00000005, /* EMC_EINPUT */
+ 0x00000004, /* EMC_EINPUT */
0x00000004, /* EMC_EINPUT_DURATION */
- 0x00070000, /* EMC_DLL_XFORM_DQS0 */
- 0x0000000a, /* EMC_QSAFE */
+ 0x00078000, /* EMC_DLL_XFORM_DQS0 */
+ 0x00000009, /* EMC_QSAFE */
0x00000000, /* EMC_DLL_XFORM_QUSE0 */
- 0x0000000c, /* EMC_RDV */
+ 0x0000000d, /* EMC_RDV */
0x00249249, /* EMC_XM2DQSPADCTRL4 */
0x20820800, /* EMC_XM2DQSPADCTRL3 */
- 0x00070000, /* EMC_DLL_XFORM_DQ0 */
- 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+ 0x00078000, /* EMC_DLL_XFORM_DQ0 */
+ 0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
0x00000000, /* EMC_DLL_XFORM_ADDR0 */
0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
0x00000000, /* EMC_DLL_XFORM_ADDR1 */
0x00000000, /* EMC_DLL_XFORM_ADDR2 */
- 0x00070000, /* EMC_DLL_XFORM_DQS1 */
- 0x00070000, /* EMC_DLL_XFORM_DQS2 */
- 0x00070000, /* EMC_DLL_XFORM_DQS3 */
- 0x00070000, /* EMC_DLL_XFORM_DQ1 */
- 0x00070000, /* EMC_DLL_XFORM_DQ2 */
- 0x00070000, /* EMC_DLL_XFORM_DQ3 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS1 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS2 */
+ 0x00078000, /* EMC_DLL_XFORM_DQS3 */
+ 0x00078000, /* EMC_DLL_XFORM_DQ1 */
+ 0x00078000, /* EMC_DLL_XFORM_DQ2 */
+ 0x00078000, /* EMC_DLL_XFORM_DQ3 */
0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
@@ -3554,7 +3554,7 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
},
0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
- 0x7320000e, /* EMC_CFG */
+ 0x7324000e, /* EMC_CFG */
0x80001221, /* Mode Register 0 */
0x80100003, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
@@ -3591,7 +3591,7 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00010000, /* EMC_PUTERM_EXTRA */
0x00000000, /* EMC_CDB_CNTL_2 */
0x00000004, /* EMC_QRST */
- 0x0000000e, /* EMC_RDV_MASK */
+ 0x0000000f, /* EMC_RDV_MASK */
0x00000607, /* EMC_REFRESH */
0x00000000, /* EMC_BURST_REFRESH_NUM */
0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */
@@ -3635,10 +3635,10 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000000, /* EMC_XM2DQPADCTRL2 */
0x77ffc085, /* EMC_XM2CLKPADCTRL */
0x81f1f108, /* EMC_XM2COMPPADCTRL */
- 0x05057404, /* EMC_XM2VTTGENPADCTRL */
+ 0x03037504, /* EMC_XM2VTTGENPADCTRL */
0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
0x0000003f, /* EMC_DSR_VTTGEN_DRV */
- 0x00000000, /* EMC_TXDSRVTTGEN */
+ 0x00000066, /* EMC_TXDSRVTTGEN */
0x02000000, /* EMC_FBIO_SPARE */
0x00000802, /* EMC_CTT_TERM_CTRL */
0x00020000, /* EMC_ZCAL_INTERVAL */
@@ -3649,7 +3649,7 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
0x00000000, /* EMC_CTT */
0x00000000, /* EMC_CTT_DURATION */
- 0x80000d24, /* EMC_DYN_SELF_REF_CONTROL */
+ 0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */
0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
0x01000003, /* MC_EMEM_ARB_CFG */
@@ -3675,16 +3675,16 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000000, /* EMC_CDB_CNTL_1 */
0x00000004, /* EMC_FBIO_CFG6 */
0x00000007, /* EMC_QUSE */
- 0x00000005, /* EMC_EINPUT */
- 0x00000005, /* EMC_EINPUT_DURATION */
+ 0x00000004, /* EMC_EINPUT */
+ 0x00000004, /* EMC_EINPUT_DURATION */
0x00064000, /* EMC_DLL_XFORM_DQS0 */
- 0x0000000a, /* EMC_QSAFE */
+ 0x00000009, /* EMC_QSAFE */
0x00000000, /* EMC_DLL_XFORM_QUSE0 */
0x0000000d, /* EMC_RDV */
0x00249249, /* EMC_XM2DQSPADCTRL4 */
0x20820800, /* EMC_XM2DQSPADCTRL3 */
- 0x00070000, /* EMC_DLL_XFORM_DQ0 */
- 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+ 0x0007c000, /* EMC_DLL_XFORM_DQ0 */
+ 0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
0x00000000, /* EMC_DLL_XFORM_ADDR0 */
0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
@@ -3693,9 +3693,9 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00064000, /* EMC_DLL_XFORM_DQS1 */
0x00064000, /* EMC_DLL_XFORM_DQS2 */
0x00064000, /* EMC_DLL_XFORM_DQS3 */
- 0x00070000, /* EMC_DLL_XFORM_DQ1 */
- 0x00070000, /* EMC_DLL_XFORM_DQ2 */
- 0x00070000, /* EMC_DLL_XFORM_DQ3 */
+ 0x0007c000, /* EMC_DLL_XFORM_DQ1 */
+ 0x0007c000, /* EMC_DLL_XFORM_DQ2 */
+ 0x0007c000, /* EMC_DLL_XFORM_DQ3 */
0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
@@ -3707,16 +3707,16 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000000, /* EMC_CDB_CNTL_1 */
0x00000004, /* EMC_FBIO_CFG6 */
0x00000007, /* EMC_QUSE */
- 0x00000005, /* EMC_EINPUT */
- 0x00000005, /* EMC_EINPUT_DURATION */
+ 0x00000004, /* EMC_EINPUT */
+ 0x00000004, /* EMC_EINPUT_DURATION */
0x00064000, /* EMC_DLL_XFORM_DQS0 */
- 0x0000000a, /* EMC_QSAFE */
+ 0x00000009, /* EMC_QSAFE */
0x00000000, /* EMC_DLL_XFORM_QUSE0 */
0x0000000d, /* EMC_RDV */
0x00249249, /* EMC_XM2DQSPADCTRL4 */
0x20820800, /* EMC_XM2DQSPADCTRL3 */
- 0x00070000, /* EMC_DLL_XFORM_DQ0 */
- 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+ 0x0007c000, /* EMC_DLL_XFORM_DQ0 */
+ 0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
0x00000000, /* EMC_DLL_XFORM_ADDR0 */
0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
@@ -3725,9 +3725,9 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00064000, /* EMC_DLL_XFORM_DQS1 */
0x00064000, /* EMC_DLL_XFORM_DQS2 */
0x00064000, /* EMC_DLL_XFORM_DQS3 */
- 0x00070000, /* EMC_DLL_XFORM_DQ1 */
- 0x00070000, /* EMC_DLL_XFORM_DQ2 */
- 0x00070000, /* EMC_DLL_XFORM_DQ3 */
+ 0x0007c000, /* EMC_DLL_XFORM_DQ1 */
+ 0x0007c000, /* EMC_DLL_XFORM_DQ2 */
+ 0x0007c000, /* EMC_DLL_XFORM_DQ3 */
0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
@@ -3762,7 +3762,7 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
312000, /* SDRAM frequency */
1000, /* min voltage */
"pll_c", /* clock source id */
- 0x24000000, /* CLK_SOURCE_EMC */
+ 0x24000002, /* CLK_SOURCE_EMC */
99, /* number of burst_regs */
30, /* number of trim_regs (each channel) */
11, /* number of up_down_regs */
@@ -3783,14 +3783,14 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000000, /* EMC_WEXT */
0x00000004, /* EMC_WDV */
0x0000000f, /* EMC_WDV_MASK */
- 0x00000007, /* EMC_IBDLY */
+ 0x00000006, /* EMC_IBDLY */
0x00010000, /* EMC_PUTERM_EXTRA */
0x00000000, /* EMC_CDB_CNTL_2 */
0x00000004, /* EMC_QRST */
0x0000000f, /* EMC_RDV_MASK */
- 0x00000945, /* EMC_REFRESH */
+ 0x00000941, /* EMC_REFRESH */
0x00000000, /* EMC_BURST_REFRESH_NUM */
- 0x00000251, /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000250, /* EMC_PRE_REFRESH_REQ_CNT */
0x00000001, /* EMC_PDEX2WR */
0x00000008, /* EMC_PDEX2RD */
0x00000001, /* EMC_PCHG2PDEN */
@@ -3806,21 +3806,21 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000000, /* EMC_TRPAB */
0x00000004, /* EMC_TCLKSTABLE */
0x00000005, /* EMC_TCLKSTOP */
- 0x00000986, /* EMC_TREFBW */
- 0x00000006, /* EMC_QUSE_EXTRA */
+ 0x00000982, /* EMC_TREFBW */
+ 0x00000000, /* EMC_QUSE_EXTRA */
0x00000020, /* EMC_ODT_WRITE */
0x00000000, /* EMC_ODT_READ */
- 0x0000ba88, /* EMC_FBIO_CFG5 */
+ 0x00005088, /* EMC_FBIO_CFG5 */
0x002c00a0, /* EMC_CFG_DIG_DLL */
0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
- 0x00040000, /* EMC_DLL_XFORM_DQS4 */
- 0x00040000, /* EMC_DLL_XFORM_DQS5 */
- 0x00040000, /* EMC_DLL_XFORM_DQS6 */
- 0x00040000, /* EMC_DLL_XFORM_DQS7 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS4 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS5 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS6 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS7 */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE4 */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE5 */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE6 */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE7 */
0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
@@ -3831,10 +3831,10 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000000, /* EMC_XM2DQPADCTRL2 */
0x77ffc085, /* EMC_XM2CLKPADCTRL */
0x81f1f108, /* EMC_XM2COMPPADCTRL */
- 0x03035504, /* EMC_XM2VTTGENPADCTRL */
+ 0x03037504, /* EMC_XM2VTTGENPADCTRL */
0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
0x0000003f, /* EMC_DSR_VTTGEN_DRV */
- 0x00000000, /* EMC_TXDSRVTTGEN */
+ 0x0000009c, /* EMC_TXDSRVTTGEN */
0x02000000, /* EMC_FBIO_SPARE */
0x00000802, /* EMC_CTT_TERM_CTRL */
0x00020000, /* EMC_ZCAL_INTERVAL */
@@ -3845,7 +3845,7 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
0x00000000, /* EMC_CTT */
0x00000000, /* EMC_CTT_DURATION */
- 0x80001395, /* EMC_DYN_SELF_REF_CONTROL */
+ 0x8000138d, /* EMC_DYN_SELF_REF_CONTROL */
0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
0x0b000004, /* MC_EMEM_ARB_CFG */
@@ -3860,76 +3860,76 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */
0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
- 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
- 0x06040202, /* MC_EMEM_ARB_DA_TURNS */
+ 0x06030202, /* MC_EMEM_ARB_DA_TURNS */
0x000b0607, /* MC_EMEM_ARB_DA_COVERS */
0x76e50f08, /* MC_EMEM_ARB_MISC0 */
0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
},
{
0x00000000, /* EMC_CDB_CNTL_1 */
- 0x00000006, /* EMC_FBIO_CFG6 */
- 0x00000007, /* EMC_QUSE */
+ 0x00000004, /* EMC_FBIO_CFG6 */
+ 0x00000006, /* EMC_QUSE */
0x00000005, /* EMC_EINPUT */
0x00000004, /* EMC_EINPUT_DURATION */
- 0x00040000, /* EMC_DLL_XFORM_DQS0 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS0 */
0x0000000b, /* EMC_QSAFE */
- 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
- 0x0000000e, /* EMC_RDV */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE0 */
+ 0x0000000d, /* EMC_RDV */
0x00249249, /* EMC_XM2DQSPADCTRL4 */
0x20820800, /* EMC_XM2DQSPADCTRL3 */
0x00048000, /* EMC_DLL_XFORM_DQ0 */
- 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+ 0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
0x00000000, /* EMC_DLL_XFORM_ADDR0 */
- 0x00000808, /* EMC_XM2CLKPADCTRL2 */
+ 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+ 0x00004000, /* EMC_DLL_XFORM_ADDR1 */
0x00000000, /* EMC_DLL_XFORM_ADDR2 */
- 0x00040000, /* EMC_DLL_XFORM_DQS1 */
- 0x00040000, /* EMC_DLL_XFORM_DQS2 */
- 0x00040000, /* EMC_DLL_XFORM_DQS3 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS1 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS2 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS3 */
0x00048000, /* EMC_DLL_XFORM_DQ1 */
0x00048000, /* EMC_DLL_XFORM_DQ2 */
0x00048000, /* EMC_DLL_XFORM_DQ3 */
0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE1 */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE2 */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE3 */
},
{
0x00000000, /* EMC_CDB_CNTL_1 */
- 0x00000006, /* EMC_FBIO_CFG6 */
- 0x00000007, /* EMC_QUSE */
+ 0x00000004, /* EMC_FBIO_CFG6 */
+ 0x00000006, /* EMC_QUSE */
0x00000005, /* EMC_EINPUT */
0x00000004, /* EMC_EINPUT_DURATION */
- 0x00040000, /* EMC_DLL_XFORM_DQS0 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS0 */
0x0000000b, /* EMC_QSAFE */
- 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
- 0x0000000e, /* EMC_RDV */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE0 */
+ 0x0000000d, /* EMC_RDV */
0x00249249, /* EMC_XM2DQSPADCTRL4 */
0x20820800, /* EMC_XM2DQSPADCTRL3 */
0x00048000, /* EMC_DLL_XFORM_DQ0 */
- 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+ 0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
0x00000000, /* EMC_DLL_XFORM_ADDR0 */
- 0x00000808, /* EMC_XM2CLKPADCTRL2 */
+ 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+ 0x00004000, /* EMC_DLL_XFORM_ADDR1 */
0x00000000, /* EMC_DLL_XFORM_ADDR2 */
- 0x00040000, /* EMC_DLL_XFORM_DQS1 */
- 0x00040000, /* EMC_DLL_XFORM_DQS2 */
- 0x00040000, /* EMC_DLL_XFORM_DQS3 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS1 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS2 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS3 */
0x00048000, /* EMC_DLL_XFORM_DQ1 */
0x00048000, /* EMC_DLL_XFORM_DQ2 */
0x00048000, /* EMC_DLL_XFORM_DQ3 */
0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE1 */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE2 */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE3 */
},
{
0x00000140, /* MC_PTSA_GRANT_DECREMENT */
@@ -3946,7 +3946,7 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
},
0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
- 0x5320000e, /* EMC_CFG */
+ 0x5300000e, /* EMC_CFG */
0x80000321, /* Mode Register 0 */
0x80100002, /* Mode Register 1 */
0x80200000, /* Mode Register 2 */
@@ -3979,12 +3979,12 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000000, /* EMC_WEXT */
0x00000004, /* EMC_WDV */
0x0000000f, /* EMC_WDV_MASK */
- 0x00000007, /* EMC_IBDLY */
+ 0x00000006, /* EMC_IBDLY */
0x00010000, /* EMC_PUTERM_EXTRA */
0x00000000, /* EMC_CDB_CNTL_2 */
0x00000004, /* EMC_QRST */
0x00000010, /* EMC_RDV_MASK */
- 0x00000c2f, /* EMC_REFRESH */
+ 0x00000c2e, /* EMC_REFRESH */
0x00000000, /* EMC_BURST_REFRESH_NUM */
0x0000030b, /* EMC_PRE_REFRESH_REQ_CNT */
0x00000001, /* EMC_PDEX2WR */
@@ -4002,21 +4002,21 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000000, /* EMC_TRPAB */
0x00000004, /* EMC_TCLKSTABLE */
0x00000005, /* EMC_TCLKSTOP */
- 0x00000c70, /* EMC_TREFBW */
- 0x00000006, /* EMC_QUSE_EXTRA */
+ 0x00000c6f, /* EMC_TREFBW */
+ 0x00000000, /* EMC_QUSE_EXTRA */
0x00000020, /* EMC_ODT_WRITE */
0x00000000, /* EMC_ODT_READ */
- 0x0000ba88, /* EMC_FBIO_CFG5 */
+ 0x00005088, /* EMC_FBIO_CFG5 */
0x002c0080, /* EMC_CFG_DIG_DLL */
0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
- 0x00028000, /* EMC_DLL_XFORM_DQS4 */
- 0x00028000, /* EMC_DLL_XFORM_DQS5 */
- 0x00028000, /* EMC_DLL_XFORM_DQS6 */
- 0x00028000, /* EMC_DLL_XFORM_DQS7 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS4 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS5 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS6 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS7 */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE4 */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE5 */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE6 */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE7 */
0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
@@ -4027,10 +4027,10 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000000, /* EMC_XM2DQPADCTRL2 */
0x77ffc085, /* EMC_XM2CLKPADCTRL */
0x81f1f108, /* EMC_XM2COMPPADCTRL */
- 0x03035504, /* EMC_XM2VTTGENPADCTRL */
+ 0x03037504, /* EMC_XM2VTTGENPADCTRL */
0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
0x0000003f, /* EMC_DSR_VTTGEN_DRV */
- 0x00000000, /* EMC_TXDSRVTTGEN */
+ 0x000000cc, /* EMC_TXDSRVTTGEN */
0x02000000, /* EMC_FBIO_SPARE */
0x00000802, /* EMC_CTT_TERM_CTRL */
0x00020000, /* EMC_ZCAL_INTERVAL */
@@ -4041,7 +4041,7 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
0x00000000, /* EMC_CTT */
0x00000000, /* EMC_CTT_DURATION */
- 0x80001944, /* EMC_DYN_SELF_REF_CONTROL */
+ 0x80001941, /* EMC_DYN_SELF_REF_CONTROL */
0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
0x02000006, /* MC_EMEM_ARB_CFG */
@@ -4065,26 +4065,26 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
},
{
0x00000000, /* EMC_CDB_CNTL_1 */
- 0x00000006, /* EMC_FBIO_CFG6 */
- 0x00000007, /* EMC_QUSE */
+ 0x00000004, /* EMC_FBIO_CFG6 */
+ 0x00000006, /* EMC_QUSE */
0x00000005, /* EMC_EINPUT */
0x00000004, /* EMC_EINPUT_DURATION */
- 0x00028000, /* EMC_DLL_XFORM_DQS0 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS0 */
0x0000000c, /* EMC_QSAFE */
- 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE0 */
0x0000000e, /* EMC_RDV */
0x00249249, /* EMC_XM2DQSPADCTRL4 */
0x20820800, /* EMC_XM2DQSPADCTRL3 */
0x00030000, /* EMC_DLL_XFORM_DQ0 */
- 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
- 0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+ 0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
+ 0x00004000, /* EMC_DLL_XFORM_ADDR0 */
0x00000808, /* EMC_XM2CLKPADCTRL2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
0x00000000, /* EMC_DLL_XFORM_ADDR1 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR2 */
- 0x00028000, /* EMC_DLL_XFORM_DQS1 */
- 0x00028000, /* EMC_DLL_XFORM_DQS2 */
- 0x00028000, /* EMC_DLL_XFORM_DQS3 */
+ 0x00004000, /* EMC_DLL_XFORM_ADDR2 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS1 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS2 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS3 */
0x00030000, /* EMC_DLL_XFORM_DQ1 */
0x00030000, /* EMC_DLL_XFORM_DQ2 */
0x00030000, /* EMC_DLL_XFORM_DQ3 */
@@ -4097,35 +4097,35 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
},
{
0x00000000, /* EMC_CDB_CNTL_1 */
- 0x00000006, /* EMC_FBIO_CFG6 */
- 0x00000007, /* EMC_QUSE */
+ 0x00000004, /* EMC_FBIO_CFG6 */
+ 0x00000006, /* EMC_QUSE */
0x00000005, /* EMC_EINPUT */
0x00000004, /* EMC_EINPUT_DURATION */
- 0x00028000, /* EMC_DLL_XFORM_DQS0 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS0 */
0x0000000c, /* EMC_QSAFE */
0x00000000, /* EMC_DLL_XFORM_QUSE0 */
0x0000000e, /* EMC_RDV */
0x00249249, /* EMC_XM2DQSPADCTRL4 */
0x20820800, /* EMC_XM2DQSPADCTRL3 */
0x00030000, /* EMC_DLL_XFORM_DQ0 */
- 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
- 0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+ 0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
+ 0x00004000, /* EMC_DLL_XFORM_ADDR0 */
0x00000808, /* EMC_XM2CLKPADCTRL2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
0x00000000, /* EMC_DLL_XFORM_ADDR1 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR2 */
- 0x00028000, /* EMC_DLL_XFORM_DQS1 */
- 0x00028000, /* EMC_DLL_XFORM_DQS2 */
- 0x00028000, /* EMC_DLL_XFORM_DQS3 */
+ 0x00004000, /* EMC_DLL_XFORM_ADDR2 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS1 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS2 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS3 */
0x00030000, /* EMC_DLL_XFORM_DQ1 */
0x00030000, /* EMC_DLL_XFORM_DQ2 */
0x00030000, /* EMC_DLL_XFORM_DQ3 */
0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE1 */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE2 */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE3 */
},
{
0x000000d1, /* MC_PTSA_GRANT_DECREMENT */
@@ -4142,7 +4142,7 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
},
0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
- 0x53200006, /* EMC_CFG */
+ 0x53000006, /* EMC_CFG */
0x80000731, /* Mode Register 0 */
0x80100002, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
@@ -4160,11 +4160,11 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
11, /* number of up_down_regs */
{
0x00000014, /* EMC_RC */
- 0x00000074, /* EMC_RFC */
+ 0x00000073, /* EMC_RFC */
0x00000000, /* EMC_RFC_SLR */
0x0000000e, /* EMC_RAS */
0x00000005, /* EMC_RP */
- 0x00000005, /* EMC_R2W */
+ 0x00000006, /* EMC_R2W */
0x00000009, /* EMC_W2R */
0x00000002, /* EMC_R2P */
0x0000000c, /* EMC_W2P */
@@ -4178,11 +4178,11 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000007, /* EMC_IBDLY */
0x00010000, /* EMC_PUTERM_EXTRA */
0x00000000, /* EMC_CDB_CNTL_2 */
- 0x00000004, /* EMC_QRST */
- 0x00000010, /* EMC_RDV_MASK */
- 0x00000d79, /* EMC_REFRESH */
+ 0x00000005, /* EMC_QRST */
+ 0x00000011, /* EMC_RDV_MASK */
+ 0x00000d76, /* EMC_REFRESH */
0x00000000, /* EMC_BURST_REFRESH_NUM */
- 0x0000035e, /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x0000035d, /* EMC_PRE_REFRESH_REQ_CNT */
0x00000001, /* EMC_PDEX2WR */
0x00000009, /* EMC_PDEX2RD */
0x00000001, /* EMC_PCHG2PDEN */
@@ -4194,39 +4194,39 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000004, /* EMC_TCKE */
0x00000004, /* EMC_TCKESR */
0x00000004, /* EMC_TPD */
- 0x00000013, /* EMC_TFAW */
+ 0x00000012, /* EMC_TFAW */
0x00000000, /* EMC_TRPAB */
0x00000004, /* EMC_TCLKSTABLE */
0x00000005, /* EMC_TCLKSTOP */
- 0x00000dba, /* EMC_TREFBW */
- 0x00000006, /* EMC_QUSE_EXTRA */
+ 0x00000db6, /* EMC_TREFBW */
+ 0x00000000, /* EMC_QUSE_EXTRA */
0x00000020, /* EMC_ODT_WRITE */
0x00000000, /* EMC_ODT_READ */
- 0x0000ba88, /* EMC_FBIO_CFG5 */
+ 0x00005088, /* EMC_FBIO_CFG5 */
0x002c0080, /* EMC_CFG_DIG_DLL */
0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
- 0x00020000, /* EMC_DLL_XFORM_DQS4 */
- 0x00020000, /* EMC_DLL_XFORM_DQS5 */
- 0x00020000, /* EMC_DLL_XFORM_DQS6 */
- 0x00020000, /* EMC_DLL_XFORM_DQS7 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS4 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS5 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS6 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS7 */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE4 */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE5 */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE6 */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE7 */
0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
0x001112a0, /* EMC_XM2CMDPADCTRL */
0x00000000, /* EMC_XM2CMDPADCTRL4 */
- 0x0000013d, /* EMC_XM2DQSPADCTRL2 */
+ 0x0001013d, /* EMC_XM2DQSPADCTRL2 */
0x00000000, /* EMC_XM2DQPADCTRL2 */
0x77ffc085, /* EMC_XM2CLKPADCTRL */
0x81f1f108, /* EMC_XM2COMPPADCTRL */
- 0x03035504, /* EMC_XM2VTTGENPADCTRL */
+ 0x03037504, /* EMC_XM2VTTGENPADCTRL */
0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
0x0000003f, /* EMC_DSR_VTTGEN_DRV */
- 0x00000000, /* EMC_TXDSRVTTGEN */
+ 0x000000e1, /* EMC_TXDSRVTTGEN */
0x02000000, /* EMC_FBIO_SPARE */
0x00000802, /* EMC_CTT_TERM_CTRL */
0x00020000, /* EMC_ZCAL_INTERVAL */
@@ -4237,7 +4237,7 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
0x00000000, /* EMC_CTT */
0x00000000, /* EMC_CTT_DURATION */
- 0x80001bc7, /* EMC_DYN_SELF_REF_CONTROL */
+ 0x80001bc0, /* EMC_DYN_SELF_REF_CONTROL */
0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
0x0c000006, /* MC_EMEM_ARB_CFG */
@@ -4246,82 +4246,82 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000003, /* MC_EMEM_ARB_TIMING_RP */
0x0000000b, /* MC_EMEM_ARB_TIMING_RC */
0x00000006, /* MC_EMEM_ARB_TIMING_RAS */
- 0x00000009, /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000008, /* MC_EMEM_ARB_TIMING_FAW */
0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
- 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000005, /* MC_EMEM_ARB_TIMING_R2W */
0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
- 0x06040202, /* MC_EMEM_ARB_DA_TURNS */
+ 0x06050202, /* MC_EMEM_ARB_DA_TURNS */
0x000f080b, /* MC_EMEM_ARB_DA_COVERS */
0x74c7150c, /* MC_EMEM_ARB_MISC0 */
0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
},
{
0x00000000, /* EMC_CDB_CNTL_1 */
- 0x00000006, /* EMC_FBIO_CFG6 */
+ 0x00000004, /* EMC_FBIO_CFG6 */
0x00000007, /* EMC_QUSE */
- 0x00000005, /* EMC_EINPUT */
+ 0x00000006, /* EMC_EINPUT */
0x00000004, /* EMC_EINPUT_DURATION */
- 0x00020000, /* EMC_DLL_XFORM_DQS0 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS0 */
0x0000000c, /* EMC_QSAFE */
- 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
- 0x0000000e, /* EMC_RDV */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE0 */
+ 0x0000000f, /* EMC_RDV */
0x00249249, /* EMC_XM2DQSPADCTRL4 */
0x20820800, /* EMC_XM2DQSPADCTRL3 */
- 0x00028000, /* EMC_DLL_XFORM_DQ0 */
- 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
- 0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+ 0x00034000, /* EMC_DLL_XFORM_DQ0 */
+ 0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
+ 0x00004000, /* EMC_DLL_XFORM_ADDR0 */
0x00000808, /* EMC_XM2CLKPADCTRL2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
0x00000000, /* EMC_DLL_XFORM_ADDR1 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR2 */
- 0x00020000, /* EMC_DLL_XFORM_DQS1 */
- 0x00020000, /* EMC_DLL_XFORM_DQS2 */
- 0x00020000, /* EMC_DLL_XFORM_DQS3 */
- 0x00028000, /* EMC_DLL_XFORM_DQ1 */
- 0x00028000, /* EMC_DLL_XFORM_DQ2 */
- 0x00028000, /* EMC_DLL_XFORM_DQ3 */
+ 0x00004000, /* EMC_DLL_XFORM_ADDR2 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS1 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS2 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS3 */
+ 0x00034000, /* EMC_DLL_XFORM_DQ1 */
+ 0x00034000, /* EMC_DLL_XFORM_DQ2 */
+ 0x00034000, /* EMC_DLL_XFORM_DQ3 */
0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE1 */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE2 */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE3 */
},
{
0x00000000, /* EMC_CDB_CNTL_1 */
- 0x00000006, /* EMC_FBIO_CFG6 */
+ 0x00000004, /* EMC_FBIO_CFG6 */
0x00000007, /* EMC_QUSE */
- 0x00000005, /* EMC_EINPUT */
+ 0x00000006, /* EMC_EINPUT */
0x00000004, /* EMC_EINPUT_DURATION */
- 0x00020000, /* EMC_DLL_XFORM_DQS0 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS0 */
0x0000000c, /* EMC_QSAFE */
- 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
- 0x0000000e, /* EMC_RDV */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE0 */
+ 0x0000000f, /* EMC_RDV */
0x00249249, /* EMC_XM2DQSPADCTRL4 */
0x20820800, /* EMC_XM2DQSPADCTRL3 */
- 0x00028000, /* EMC_DLL_XFORM_DQ0 */
- 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
- 0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+ 0x00034000, /* EMC_DLL_XFORM_DQ0 */
+ 0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
+ 0x00004000, /* EMC_DLL_XFORM_ADDR0 */
0x00000808, /* EMC_XM2CLKPADCTRL2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR2 */
- 0x00020000, /* EMC_DLL_XFORM_DQS1 */
- 0x00020000, /* EMC_DLL_XFORM_DQS2 */
- 0x00020000, /* EMC_DLL_XFORM_DQS3 */
- 0x00028000, /* EMC_DLL_XFORM_DQ1 */
- 0x00028000, /* EMC_DLL_XFORM_DQ2 */
- 0x00028000, /* EMC_DLL_XFORM_DQ3 */
+ 0x00004000, /* EMC_DLL_XFORM_ADDR1 */
+ 0x00004000, /* EMC_DLL_XFORM_ADDR2 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS1 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS2 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS3 */
+ 0x00034000, /* EMC_DLL_XFORM_DQ1 */
+ 0x00034000, /* EMC_DLL_XFORM_DQ2 */
+ 0x00034000, /* EMC_DLL_XFORM_DQ3 */
0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE1 */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE2 */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE3 */
},
{
0x000000e6, /* MC_PTSA_GRANT_DECREMENT */
@@ -4338,8 +4338,8 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
},
0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
- 0x53200006, /* EMC_CFG */
- 0x80000731, /* Mode Register 0 */
+ 0x53000006, /* EMC_CFG */
+ 0x80000741, /* Mode Register 0 */
0x80100002, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
@@ -4376,14 +4376,14 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000000, /* EMC_CDB_CNTL_2 */
0x00000006, /* EMC_QRST */
0x00000012, /* EMC_RDV_MASK */
- 0x00000fde, /* EMC_REFRESH */
+ 0x00000fd6, /* EMC_REFRESH */
0x00000000, /* EMC_BURST_REFRESH_NUM */
- 0x000003f7, /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x000003f5, /* EMC_PRE_REFRESH_REQ_CNT */
0x00000002, /* EMC_PDEX2WR */
0x0000000b, /* EMC_PDEX2RD */
0x00000001, /* EMC_PCHG2PDEN */
0x00000000, /* EMC_ACT2PDEN */
- 0x00000085, /* EMC_AR2PDEN */
+ 0x00000084, /* EMC_AR2PDEN */
0x00000012, /* EMC_RW2PDEN */
0x0000008f, /* EMC_TXSR */
0x00000200, /* EMC_TXSRDLL */
@@ -4394,17 +4394,17 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000000, /* EMC_TRPAB */
0x00000005, /* EMC_TCLKSTABLE */
0x00000006, /* EMC_TCLKSTOP */
- 0x0000101f, /* EMC_TREFBW */
- 0x00000008, /* EMC_QUSE_EXTRA */
+ 0x00001017, /* EMC_TREFBW */
+ 0x00000000, /* EMC_QUSE_EXTRA */
0x00000020, /* EMC_ODT_WRITE */
0x00000000, /* EMC_ODT_READ */
- 0x0000ba88, /* EMC_FBIO_CFG5 */
+ 0x00005088, /* EMC_FBIO_CFG5 */
0xf0120091, /* EMC_CFG_DIG_DLL */
0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
- 0x00000009, /* EMC_DLL_XFORM_DQS4 */
- 0x00000009, /* EMC_DLL_XFORM_DQS5 */
- 0x00000009, /* EMC_DLL_XFORM_DQS6 */
- 0x00000009, /* EMC_DLL_XFORM_DQS7 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS4 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS5 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS6 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS7 */
0x00000000, /* EMC_DLL_XFORM_QUSE4 */
0x00000000, /* EMC_DLL_XFORM_QUSE5 */
0x00000000, /* EMC_DLL_XFORM_QUSE6 */
@@ -4419,21 +4419,21 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000000, /* EMC_XM2DQPADCTRL2 */
0x77ffc085, /* EMC_XM2CLKPADCTRL */
0x81f1f108, /* EMC_XM2COMPPADCTRL */
- 0x03035504, /* EMC_XM2VTTGENPADCTRL */
+ 0x07077504, /* EMC_XM2VTTGENPADCTRL */
0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
0x0000003f, /* EMC_DSR_VTTGEN_DRV */
- 0x00000000, /* EMC_TXDSRVTTGEN */
+ 0x00000108, /* EMC_TXDSRVTTGEN */
0x02000000, /* EMC_FBIO_SPARE */
0x00000802, /* EMC_CTT_TERM_CTRL */
0x00020000, /* EMC_ZCAL_INTERVAL */
0x00000100, /* EMC_ZCAL_WAIT_CNT */
- 0x0139000f, /* EMC_MRS_WAIT_CNT */
- 0x0139000f, /* EMC_MRS_WAIT_CNT2 */
+ 0x013a000f, /* EMC_MRS_WAIT_CNT */
+ 0x013a000f, /* EMC_MRS_WAIT_CNT2 */
0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
0x00000000, /* EMC_CTT */
0x00000000, /* EMC_CTT_DURATION */
- 0x80002073, /* EMC_DYN_SELF_REF_CONTROL */
+ 0x80002062, /* EMC_DYN_SELF_REF_CONTROL */
0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
0x0f000007, /* MC_EMEM_ARB_CFG */
@@ -4458,28 +4458,28 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
{
0x00000000, /* EMC_CDB_CNTL_1 */
0x00000006, /* EMC_FBIO_CFG6 */
- 0x00000009, /* EMC_QUSE */
+ 0x00000008, /* EMC_QUSE */
0x00000007, /* EMC_EINPUT */
0x00000004, /* EMC_EINPUT_DURATION */
- 0x00000009, /* EMC_DLL_XFORM_DQS0 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS0 */
0x0000000c, /* EMC_QSAFE */
0x00000000, /* EMC_DLL_XFORM_QUSE0 */
0x00000010, /* EMC_RDV */
0x00249249, /* EMC_XM2DQSPADCTRL4 */
0x20820800, /* EMC_XM2DQSPADCTRL3 */
- 0x0000400b, /* EMC_DLL_XFORM_DQ0 */
- 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
- 0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+ 0x0000000b, /* EMC_DLL_XFORM_DQ0 */
+ 0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
+ 0x00004000, /* EMC_DLL_XFORM_ADDR0 */
0x00000808, /* EMC_XM2CLKPADCTRL2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
0x00000000, /* EMC_DLL_XFORM_ADDR1 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR2 */
- 0x00000009, /* EMC_DLL_XFORM_DQS1 */
- 0x00000009, /* EMC_DLL_XFORM_DQS2 */
- 0x00000009, /* EMC_DLL_XFORM_DQS3 */
- 0x0000400b, /* EMC_DLL_XFORM_DQ1 */
- 0x0000400b, /* EMC_DLL_XFORM_DQ2 */
- 0x0000400b, /* EMC_DLL_XFORM_DQ3 */
+ 0x00004000, /* EMC_DLL_XFORM_ADDR2 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS1 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS2 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS3 */
+ 0x0000000b, /* EMC_DLL_XFORM_DQ1 */
+ 0x0000000c, /* EMC_DLL_XFORM_DQ2 */
+ 0x0000000c, /* EMC_DLL_XFORM_DQ3 */
0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
@@ -4490,28 +4490,28 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
{
0x00000000, /* EMC_CDB_CNTL_1 */
0x00000006, /* EMC_FBIO_CFG6 */
- 0x00000009, /* EMC_QUSE */
+ 0x00000008, /* EMC_QUSE */
0x00000007, /* EMC_EINPUT */
0x00000004, /* EMC_EINPUT_DURATION */
- 0x00000009, /* EMC_DLL_XFORM_DQS0 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS0 */
0x0000000c, /* EMC_QSAFE */
0x00000000, /* EMC_DLL_XFORM_QUSE0 */
0x00000010, /* EMC_RDV */
0x00249249, /* EMC_XM2DQSPADCTRL4 */
0x20820800, /* EMC_XM2DQSPADCTRL3 */
- 0x0000400b, /* EMC_DLL_XFORM_DQ0 */
- 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
- 0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+ 0x0000000b, /* EMC_DLL_XFORM_DQ0 */
+ 0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
+ 0x00004000, /* EMC_DLL_XFORM_ADDR0 */
0x00000808, /* EMC_XM2CLKPADCTRL2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
0x00000000, /* EMC_DLL_XFORM_ADDR1 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR2 */
- 0x00000009, /* EMC_DLL_XFORM_DQS1 */
- 0x00000009, /* EMC_DLL_XFORM_DQS2 */
- 0x00000009, /* EMC_DLL_XFORM_DQS3 */
- 0x0000400b, /* EMC_DLL_XFORM_DQ1 */
- 0x0000400b, /* EMC_DLL_XFORM_DQ2 */
- 0x0000400b, /* EMC_DLL_XFORM_DQ3 */
+ 0x00004000, /* EMC_DLL_XFORM_ADDR2 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS1 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS2 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS3 */
+ 0x0000000b, /* EMC_DLL_XFORM_DQ1 */
+ 0x0000000c, /* EMC_DLL_XFORM_DQ2 */
+ 0x0000000c, /* EMC_DLL_XFORM_DQ3 */
0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
@@ -4534,7 +4534,7 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
},
0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
- 0x53200004, /* EMC_CFG */
+ 0x53000004, /* EMC_CFG */
0x80000941, /* Mode Register 0 */
0x80100002, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
@@ -4567,19 +4567,19 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000000, /* EMC_WEXT */
0x00000005, /* EMC_WDV */
0x0000000f, /* EMC_WDV_MASK */
- 0x0000000b, /* EMC_IBDLY */
+ 0x0000000a, /* EMC_IBDLY */
0x00010000, /* EMC_PUTERM_EXTRA */
0x00000000, /* EMC_CDB_CNTL_2 */
0x00000007, /* EMC_QRST */
- 0x00000013, /* EMC_RDV_MASK */
- 0x000012cb, /* EMC_REFRESH */
+ 0x00000014, /* EMC_RDV_MASK */
+ 0x000012c3, /* EMC_REFRESH */
0x00000000, /* EMC_BURST_REFRESH_NUM */
- 0x000004b2, /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x000004b0, /* EMC_PRE_REFRESH_REQ_CNT */
0x00000002, /* EMC_PDEX2WR */
0x0000000d, /* EMC_PDEX2RD */
0x00000001, /* EMC_PCHG2PDEN */
0x00000000, /* EMC_ACT2PDEN */
- 0x000000a5, /* EMC_AR2PDEN */
+ 0x0000009c, /* EMC_AR2PDEN */
0x00000015, /* EMC_RW2PDEN */
0x000000a9, /* EMC_TXSR */
0x00000200, /* EMC_TXSRDLL */
@@ -4590,7 +4590,7 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000000, /* EMC_TRPAB */
0x00000006, /* EMC_TCLKSTABLE */
0x00000007, /* EMC_TCLKSTOP */
- 0x0000130b, /* EMC_TREFBW */
+ 0x00001304, /* EMC_TREFBW */
0x00000009, /* EMC_QUSE_EXTRA */
0x00000020, /* EMC_ODT_WRITE */
0x00000000, /* EMC_ODT_READ */
@@ -4601,10 +4601,10 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x0000000a, /* EMC_DLL_XFORM_DQS5 */
0x0000000a, /* EMC_DLL_XFORM_DQS6 */
0x0000000a, /* EMC_DLL_XFORM_DQS7 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE4 */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE5 */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE6 */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE7 */
0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
@@ -4618,7 +4618,7 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x07077504, /* EMC_XM2VTTGENPADCTRL */
0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
0x0000003f, /* EMC_DSR_VTTGEN_DRV */
- 0x00000000, /* EMC_TXDSRVTTGEN */
+ 0x00000138, /* EMC_TXDSRVTTGEN */
0x02000000, /* EMC_FBIO_SPARE */
0x00000802, /* EMC_CTT_TERM_CTRL */
0x00020000, /* EMC_ZCAL_INTERVAL */
@@ -4629,7 +4629,7 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
0x00000000, /* EMC_CTT */
0x00000000, /* EMC_CTT_DURATION */
- 0x80002626, /* EMC_DYN_SELF_REF_CONTROL */
+ 0x80002617, /* EMC_DYN_SELF_REF_CONTROL */
0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
0x06000009, /* MC_EMEM_ARB_CFG */
@@ -4654,22 +4654,22 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
{
0x00000000, /* EMC_CDB_CNTL_1 */
0x00000006, /* EMC_FBIO_CFG6 */
- 0x0000000a, /* EMC_QUSE */
- 0x00000007, /* EMC_EINPUT */
- 0x00000005, /* EMC_EINPUT_DURATION */
+ 0x00000009, /* EMC_QUSE */
+ 0x00000008, /* EMC_EINPUT */
+ 0x00000004, /* EMC_EINPUT_DURATION */
0x0000000a, /* EMC_DLL_XFORM_DQS0 */
0x0000000c, /* EMC_QSAFE */
- 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
- 0x00000011, /* EMC_RDV */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000012, /* EMC_RDV */
0x00249249, /* EMC_XM2DQSPADCTRL4 */
0x20820800, /* EMC_XM2DQSPADCTRL3 */
0x0000000b, /* EMC_DLL_XFORM_DQ0 */
- 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
- 0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+ 0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
+ 0x00000001, /* EMC_DLL_XFORM_ADDR0 */
0x00000808, /* EMC_XM2CLKPADCTRL2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
0x00000000, /* EMC_DLL_XFORM_ADDR1 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+ 0x00000001, /* EMC_DLL_XFORM_ADDR2 */
0x0000000a, /* EMC_DLL_XFORM_DQS1 */
0x0000000a, /* EMC_DLL_XFORM_DQS2 */
0x0000000a, /* EMC_DLL_XFORM_DQS3 */
@@ -4679,41 +4679,41 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE1 */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE2 */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE3 */
},
{
0x00000000, /* EMC_CDB_CNTL_1 */
0x00000006, /* EMC_FBIO_CFG6 */
- 0x0000000a, /* EMC_QUSE */
- 0x00000007, /* EMC_EINPUT */
- 0x00000005, /* EMC_EINPUT_DURATION */
+ 0x00000009, /* EMC_QUSE */
+ 0x00000008, /* EMC_EINPUT */
+ 0x00000004, /* EMC_EINPUT_DURATION */
0x0000000a, /* EMC_DLL_XFORM_DQS0 */
0x0000000c, /* EMC_QSAFE */
- 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
- 0x00000011, /* EMC_RDV */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000012, /* EMC_RDV */
0x00249249, /* EMC_XM2DQSPADCTRL4 */
0x20820800, /* EMC_XM2DQSPADCTRL3 */
- 0x0000000a, /* EMC_DLL_XFORM_DQ0 */
- 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
- 0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+ 0x0000000b, /* EMC_DLL_XFORM_DQ0 */
+ 0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
+ 0x00000001, /* EMC_DLL_XFORM_ADDR0 */
0x00000808, /* EMC_XM2CLKPADCTRL2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
0x00000000, /* EMC_DLL_XFORM_ADDR1 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+ 0x00000001, /* EMC_DLL_XFORM_ADDR2 */
0x0000000a, /* EMC_DLL_XFORM_DQS1 */
0x0000000a, /* EMC_DLL_XFORM_DQS2 */
0x0000000a, /* EMC_DLL_XFORM_DQS3 */
0x0000000a, /* EMC_DLL_XFORM_DQ1 */
- 0x0000000a, /* EMC_DLL_XFORM_DQ2 */
- 0x0000000a, /* EMC_DLL_XFORM_DQ3 */
+ 0x0000000b, /* EMC_DLL_XFORM_DQ2 */
+ 0x0000000b, /* EMC_DLL_XFORM_DQ3 */
0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE1 */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE2 */
+ 0x00020000, /* EMC_DLL_XFORM_QUSE3 */
},
{
0x0000013f, /* MC_PTSA_GRANT_DECREMENT */
@@ -4730,7 +4730,7 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
},
0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
- 0x53200000, /* EMC_CFG */
+ 0x53000000, /* EMC_CFG */
0x80000b61, /* Mode Register 0 */
0x80100002, /* Mode Register 1 */
0x80200010, /* Mode Register 2 */
@@ -4747,12 +4747,12 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
30, /* number of trim_regs (each channel) */
11, /* number of up_down_regs */
{
- 0x00000025, /* EMC_RC */
- 0x000000cd, /* EMC_RFC */
+ 0x00000024, /* EMC_RC */
+ 0x000000cc, /* EMC_RFC */
0x00000000, /* EMC_RFC_SLR */
0x00000019, /* EMC_RAS */
0x0000000a, /* EMC_RP */
- 0x00000009, /* EMC_R2W */
+ 0x00000008, /* EMC_R2W */
0x0000000d, /* EMC_W2R */
0x00000004, /* EMC_R2P */
0x00000013, /* EMC_W2P */
@@ -4763,21 +4763,21 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000000, /* EMC_WEXT */
0x00000006, /* EMC_WDV */
0x0000000f, /* EMC_WDV_MASK */
- 0x0000000c, /* EMC_IBDLY */
- 0x000d000a, /* EMC_PUTERM_EXTRA */
+ 0x0000000b, /* EMC_IBDLY */
+ 0x00010000, /* EMC_PUTERM_EXTRA */
0x00000000, /* EMC_CDB_CNTL_2 */
- 0x00000009, /* EMC_QRST */
+ 0x00000008, /* EMC_QRST */
0x00000016, /* EMC_RDV_MASK */
- 0x000017ee, /* EMC_REFRESH */
+ 0x000017e1, /* EMC_REFRESH */
0x00000000, /* EMC_BURST_REFRESH_NUM */
- 0x000005fb, /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x000005f8, /* EMC_PRE_REFRESH_REQ_CNT */
0x00000003, /* EMC_PDEX2WR */
- 0x00000012, /* EMC_PDEX2RD */
+ 0x00000011, /* EMC_PDEX2RD */
0x00000001, /* EMC_PCHG2PDEN */
0x00000000, /* EMC_ACT2PDEN */
0x000000c6, /* EMC_AR2PDEN */
0x00000018, /* EMC_RW2PDEN */
- 0x000000d7, /* EMC_TXSR */
+ 0x000000d6, /* EMC_TXSR */
0x00000200, /* EMC_TXSRDLL */
0x00000005, /* EMC_TCKE */
0x00000005, /* EMC_TCKESR */
@@ -4786,21 +4786,21 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000000, /* EMC_TRPAB */
0x00000007, /* EMC_TCLKSTABLE */
0x00000008, /* EMC_TCLKSTOP */
- 0x0000182f, /* EMC_TREFBW */
- 0x0000000b, /* EMC_QUSE_EXTRA */
+ 0x00001822, /* EMC_TREFBW */
+ 0x00000000, /* EMC_QUSE_EXTRA */
0x80000000, /* EMC_ODT_WRITE */
0x00000000, /* EMC_ODT_READ */
- 0x0000ba88, /* EMC_FBIO_CFG5 */
+ 0x00005088, /* EMC_FBIO_CFG5 */
0xf0070191, /* EMC_CFG_DIG_DLL */
0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
0x00000007, /* EMC_DLL_XFORM_DQS4 */
0x00000007, /* EMC_DLL_XFORM_DQS5 */
0x00000007, /* EMC_DLL_XFORM_DQS6 */
0x00000007, /* EMC_DLL_XFORM_DQS7 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+ 0x00008000, /* EMC_DLL_XFORM_QUSE4 */
+ 0x00008000, /* EMC_DLL_XFORM_QUSE5 */
+ 0x00008000, /* EMC_DLL_XFORM_QUSE6 */
+ 0x00008000, /* EMC_DLL_XFORM_QUSE7 */
0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
@@ -4811,10 +4811,10 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000000, /* EMC_XM2DQPADCTRL2 */
0x77ffc085, /* EMC_XM2CLKPADCTRL */
0x81f1f108, /* EMC_XM2COMPPADCTRL */
- 0x07076604, /* EMC_XM2VTTGENPADCTRL */
+ 0x07077504, /* EMC_XM2VTTGENPADCTRL */
0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
0x0000003f, /* EMC_DSR_VTTGEN_DRV */
- 0x00000000, /* EMC_TXDSRVTTGEN */
+ 0x0000018c, /* EMC_TXDSRVTTGEN */
0x02000000, /* EMC_FBIO_SPARE */
0x00000802, /* EMC_CTT_TERM_CTRL */
0x00020000, /* EMC_ZCAL_INTERVAL */
@@ -4825,7 +4825,7 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
0x00000000, /* EMC_CTT */
0x00000000, /* EMC_CTT_DURATION */
- 0x8000302b, /* EMC_DYN_SELF_REF_CONTROL */
+ 0x80003012, /* EMC_DYN_SELF_REF_CONTROL */
0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
0x0e00000b, /* MC_EMEM_ARB_CFG */
@@ -4850,13 +4850,13 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
{
0x00000000, /* EMC_CDB_CNTL_1 */
0x00000006, /* EMC_FBIO_CFG6 */
- 0x0000000d, /* EMC_QUSE */
- 0x00000009, /* EMC_EINPUT */
- 0x00000005, /* EMC_EINPUT_DURATION */
+ 0x0000000a, /* EMC_QUSE */
+ 0x00000008, /* EMC_EINPUT */
+ 0x00000006, /* EMC_EINPUT_DURATION */
0x00000007, /* EMC_DLL_XFORM_DQS0 */
0x0000000d, /* EMC_QSAFE */
- 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
- 0x00000015, /* EMC_RDV */
+ 0x00008000, /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000014, /* EMC_RDV */
0x00249249, /* EMC_XM2DQSPADCTRL4 */
0x20820800, /* EMC_XM2DQSPADCTRL3 */
0x0000400a, /* EMC_DLL_XFORM_DQ0 */
@@ -4870,25 +4870,25 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000007, /* EMC_DLL_XFORM_DQS2 */
0x00000007, /* EMC_DLL_XFORM_DQS3 */
0x0000400a, /* EMC_DLL_XFORM_DQ1 */
- 0x0000400c, /* EMC_DLL_XFORM_DQ2 */
+ 0x0000400a, /* EMC_DLL_XFORM_DQ2 */
0x0000400a, /* EMC_DLL_XFORM_DQ3 */
0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+ 0x00008000, /* EMC_DLL_XFORM_QUSE1 */
+ 0x00008000, /* EMC_DLL_XFORM_QUSE2 */
+ 0x00008000, /* EMC_DLL_XFORM_QUSE3 */
},
{
0x00000000, /* EMC_CDB_CNTL_1 */
0x00000006, /* EMC_FBIO_CFG6 */
- 0x0000000d, /* EMC_QUSE */
- 0x00000009, /* EMC_EINPUT */
- 0x00000005, /* EMC_EINPUT_DURATION */
+ 0x0000000a, /* EMC_QUSE */
+ 0x00000008, /* EMC_EINPUT */
+ 0x00000006, /* EMC_EINPUT_DURATION */
0x00000007, /* EMC_DLL_XFORM_DQS0 */
0x0000000d, /* EMC_QSAFE */
- 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
- 0x00000015, /* EMC_RDV */
+ 0x00008000, /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000014, /* EMC_RDV */
0x00249249, /* EMC_XM2DQSPADCTRL4 */
0x20820800, /* EMC_XM2DQSPADCTRL3 */
0x0000400a, /* EMC_DLL_XFORM_DQ0 */
@@ -4902,14 +4902,14 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000007, /* EMC_DLL_XFORM_DQS2 */
0x00000007, /* EMC_DLL_XFORM_DQS3 */
0x0000400a, /* EMC_DLL_XFORM_DQ1 */
- 0x0000400c, /* EMC_DLL_XFORM_DQ2 */
+ 0x0000400a, /* EMC_DLL_XFORM_DQ2 */
0x0000400a, /* EMC_DLL_XFORM_DQ3 */
0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+ 0x00008000, /* EMC_DLL_XFORM_QUSE1 */
+ 0x00008000, /* EMC_DLL_XFORM_QUSE2 */
+ 0x00008000, /* EMC_DLL_XFORM_QUSE3 */
},
{
0x00000196, /* MC_PTSA_GRANT_DECREMENT */
@@ -4926,8 +4926,8 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
},
0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
- 0x53300000, /* EMC_CFG */
- 0x80000d05, /* Mode Register 0 */
+ 0x53000000, /* EMC_CFG */
+ 0x80000d71, /* Mode Register 0 */
0x80100002, /* Mode Register 1 */
0x80200418, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
@@ -4944,7 +4944,7 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
11, /* number of up_down_regs */
{
0x0000002a, /* EMC_RC */
- 0x000000e9, /* EMC_RFC */
+ 0x000000e8, /* EMC_RFC */
0x00000000, /* EMC_RFC_SLR */
0x0000001d, /* EMC_RAS */
0x0000000b, /* EMC_RP */
@@ -4963,40 +4963,40 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00010000, /* EMC_PUTERM_EXTRA */
0x00000000, /* EMC_CDB_CNTL_2 */
0x0000000a, /* EMC_QRST */
- 0x00000017, /* EMC_RDV_MASK */
- 0x00001b33, /* EMC_REFRESH */
+ 0x00000018, /* EMC_RDV_MASK */
+ 0x00001b2c, /* EMC_REFRESH */
0x00000000, /* EMC_BURST_REFRESH_NUM */
- 0x000006cc, /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x000006cb, /* EMC_PRE_REFRESH_REQ_CNT */
0x00000004, /* EMC_PDEX2WR */
0x00000014, /* EMC_PDEX2RD */
0x00000001, /* EMC_PCHG2PDEN */
0x00000000, /* EMC_ACT2PDEN */
0x000000e0, /* EMC_AR2PDEN */
0x0000001b, /* EMC_RW2PDEN */
- 0x000000f4, /* EMC_TXSR */
+ 0x000000f3, /* EMC_TXSR */
0x00000200, /* EMC_TXSRDLL */
0x00000006, /* EMC_TCKE */
0x00000006, /* EMC_TCKESR */
0x00000006, /* EMC_TPD */
- 0x00000025, /* EMC_TFAW */
+ 0x00000024, /* EMC_TFAW */
0x00000000, /* EMC_TRPAB */
0x00000008, /* EMC_TCLKSTABLE */
0x00000009, /* EMC_TCLKSTOP */
- 0x00001b74, /* EMC_TREFBW */
+ 0x00001b6c, /* EMC_TREFBW */
0x00000000, /* EMC_QUSE_EXTRA */
0x80000000, /* EMC_ODT_WRITE */
0x00000000, /* EMC_ODT_READ */
0x00005088, /* EMC_FBIO_CFG5 */
0xf0040191, /* EMC_CFG_DIG_DLL */
0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
- 0x00000007, /* EMC_DLL_XFORM_DQS4 */
- 0x00000007, /* EMC_DLL_XFORM_DQS5 */
- 0x00000007, /* EMC_DLL_XFORM_DQS6 */
- 0x00000007, /* EMC_DLL_XFORM_DQS7 */
- 0x00018007, /* EMC_DLL_XFORM_QUSE4 */
- 0x00018007, /* EMC_DLL_XFORM_QUSE5 */
- 0x00018007, /* EMC_DLL_XFORM_QUSE6 */
- 0x00018007, /* EMC_DLL_XFORM_QUSE7 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS4 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS5 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS6 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS7 */
+ 0x00018000, /* EMC_DLL_XFORM_QUSE4 */
+ 0x00018000, /* EMC_DLL_XFORM_QUSE5 */
+ 0x00018000, /* EMC_DLL_XFORM_QUSE6 */
+ 0x00018000, /* EMC_DLL_XFORM_QUSE7 */
0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
@@ -5010,18 +5010,18 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x07077504, /* EMC_XM2VTTGENPADCTRL */
0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
0x0000003f, /* EMC_DSR_VTTGEN_DRV */
- 0x00000000, /* EMC_TXDSRVTTGEN */
+ 0x000001c2, /* EMC_TXDSRVTTGEN */
0x02000000, /* EMC_FBIO_SPARE */
0x00000802, /* EMC_CTT_TERM_CTRL */
0x00020000, /* EMC_ZCAL_INTERVAL */
0x00000120, /* EMC_ZCAL_WAIT_CNT */
- 0x00d5000f, /* EMC_MRS_WAIT_CNT */
- 0x00d5000f, /* EMC_MRS_WAIT_CNT2 */
+ 0x00d6000f, /* EMC_MRS_WAIT_CNT */
+ 0x00d6000f, /* EMC_MRS_WAIT_CNT2 */
0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
0x00000000, /* EMC_CTT */
0x00000000, /* EMC_CTT_DURATION */
- 0x8000368a, /* EMC_DYN_SELF_REF_CONTROL */
+ 0x8000367c, /* EMC_DYN_SELF_REF_CONTROL */
0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
0x0800000d, /* MC_EMEM_ARB_CFG */
@@ -5030,7 +5030,7 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x00000006, /* MC_EMEM_ARB_TIMING_RP */
0x00000015, /* MC_EMEM_ARB_TIMING_RC */
0x0000000e, /* MC_EMEM_ARB_TIMING_RAS */
- 0x00000012, /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000011, /* MC_EMEM_ARB_TIMING_FAW */
0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
0x00000004, /* MC_EMEM_ARB_TIMING_RAP2PRE */
0x0000000e, /* MC_EMEM_ARB_TIMING_WAP2PRE */
@@ -5049,31 +5049,31 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x0000000c, /* EMC_QUSE */
0x0000000a, /* EMC_EINPUT */
0x00000006, /* EMC_EINPUT_DURATION */
- 0x00000007, /* EMC_DLL_XFORM_DQS0 */
+ 0x00000009, /* EMC_DLL_XFORM_DQS0 */
0x0000000d, /* EMC_QSAFE */
- 0x00018007, /* EMC_DLL_XFORM_QUSE0 */
- 0x00000015, /* EMC_RDV */
+ 0x00018000, /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000016, /* EMC_RDV */
0x00249249, /* EMC_XM2DQSPADCTRL4 */
0x20820800, /* EMC_XM2DQSPADCTRL3 */
- 0x00000007, /* EMC_DLL_XFORM_DQ0 */
- 0xa0f10202, /* EMC_AUTO_CAL_CONFIG */
+ 0x0000400a, /* EMC_DLL_XFORM_DQ0 */
+ 0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
0x00000000, /* EMC_DLL_XFORM_ADDR0 */
0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
0x00000000, /* EMC_DLL_XFORM_ADDR1 */
0x00000000, /* EMC_DLL_XFORM_ADDR2 */
- 0x00000007, /* EMC_DLL_XFORM_DQS1 */
- 0x00000007, /* EMC_DLL_XFORM_DQS2 */
- 0x00000007, /* EMC_DLL_XFORM_DQS3 */
- 0x00000007, /* EMC_DLL_XFORM_DQ1 */
- 0x00000007, /* EMC_DLL_XFORM_DQ2 */
- 0x00000008, /* EMC_DLL_XFORM_DQ3 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS1 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS2 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS3 */
+ 0x0000400a, /* EMC_DLL_XFORM_DQ1 */
+ 0x0000400a, /* EMC_DLL_XFORM_DQ2 */
+ 0x0000400a, /* EMC_DLL_XFORM_DQ3 */
0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
- 0x00018007, /* EMC_DLL_XFORM_QUSE1 */
- 0x00018007, /* EMC_DLL_XFORM_QUSE2 */
- 0x00018007, /* EMC_DLL_XFORM_QUSE3 */
+ 0x00018000, /* EMC_DLL_XFORM_QUSE1 */
+ 0x00018000, /* EMC_DLL_XFORM_QUSE2 */
+ 0x00018000, /* EMC_DLL_XFORM_QUSE3 */
},
{
0x00000000, /* EMC_CDB_CNTL_1 */
@@ -5081,31 +5081,31 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x0000000c, /* EMC_QUSE */
0x0000000a, /* EMC_EINPUT */
0x00000006, /* EMC_EINPUT_DURATION */
- 0x00000007, /* EMC_DLL_XFORM_DQS0 */
+ 0x00000009, /* EMC_DLL_XFORM_DQS0 */
0x0000000d, /* EMC_QSAFE */
- 0x00018007, /* EMC_DLL_XFORM_QUSE0 */
- 0x00000015, /* EMC_RDV */
+ 0x00018000, /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000016, /* EMC_RDV */
0x00249249, /* EMC_XM2DQSPADCTRL4 */
0x20820800, /* EMC_XM2DQSPADCTRL3 */
- 0x00000007, /* EMC_DLL_XFORM_DQ0 */
+ 0x0000400a, /* EMC_DLL_XFORM_DQ0 */
0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
0x00000000, /* EMC_DLL_XFORM_ADDR0 */
0x00000a0a, /* EMC_XM2CLKPADCTRL2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
0x00000000, /* EMC_DLL_XFORM_ADDR1 */
0x00000000, /* EMC_DLL_XFORM_ADDR2 */
- 0x00000007, /* EMC_DLL_XFORM_DQS1 */
- 0x00000007, /* EMC_DLL_XFORM_DQS2 */
- 0x00000007, /* EMC_DLL_XFORM_DQS3 */
- 0x00000007, /* EMC_DLL_XFORM_DQ1 */
- 0x00000007, /* EMC_DLL_XFORM_DQ2 */
- 0x00000008, /* EMC_DLL_XFORM_DQ3 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS1 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS2 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS3 */
+ 0x0000400a, /* EMC_DLL_XFORM_DQ1 */
+ 0x0000400a, /* EMC_DLL_XFORM_DQ2 */
+ 0x0000400a, /* EMC_DLL_XFORM_DQ3 */
0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
- 0x00018007, /* EMC_DLL_XFORM_QUSE1 */
- 0x00018007, /* EMC_DLL_XFORM_QUSE2 */
- 0x00018007, /* EMC_DLL_XFORM_QUSE3 */
+ 0x00018000, /* EMC_DLL_XFORM_QUSE1 */
+ 0x00018000, /* EMC_DLL_XFORM_QUSE2 */
+ 0x00018000, /* EMC_DLL_XFORM_QUSE3 */
},
{
0x000001cd, /* MC_PTSA_GRANT_DECREMENT */
@@ -5120,7 +5120,7 @@ static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = {
0x0060002d, /* MC_LATENCY_ALLOWANCE_EPP_0 */
0x00600060, /* MC_LATENCY_ALLOWANCE_EPP_1 */
},
- 0x0000004b, /* EMC_ZCAL_WAIT_CNT after clock change */
+ 0x0000004a, /* EMC_ZCAL_WAIT_CNT after clock change */
0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
0x53000000, /* EMC_CFG */
0x80000f15, /* Mode Register 0 */
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-24 09:06:22 +0000