Merge commit 'rel_imx_3.0.35_12.11.01_RC2' into imx_3.0.35_android_r13.4.y

Conflicts:
	drivers/mxc/vpu/mxc_vpu.c

12 files changed, 379 insertions, 163 deletions

diff --git a/arch/arm/configs/imx6_defconfig b/arch/arm/configs/imx6_defconfig
index f1bab5fe2838..f62ea0ebab7d 100644
--- a/arch/arm/configs/imx6_defconfig
+++ b/arch/arm/configs/imx6_defconfig
@@ -1848,7 +1848,7 @@ CONFIG_SND_IMX_SOC=y
 CONFIG_SND_MXC_SOC_MX2=y
 CONFIG_SND_MXC_SOC_SPDIF_DAI=y
 CONFIG_SND_SOC_IMX_SGTL5000=y
-CONFIG_SND_SOC_IMX_WM8958=y
+# CONFIG_SND_SOC_IMX_WM8958 is not set
 CONFIG_SND_SOC_IMX_WM8962=y
 CONFIG_SND_SOC_IMX_CS42888=y
 # CONFIG_SND_SOC_IMX_SI4763 is not set
@@ -1856,13 +1856,13 @@ CONFIG_SND_SOC_IMX_SPDIF=y
 CONFIG_SND_SOC_IMX_HDMI=y
 CONFIG_SND_SOC_I2C_AND_SPI=y
 # CONFIG_SND_SOC_ALL_CODECS is not set
-CONFIG_SND_SOC_WM_HUBS=y
+# CONFIG_SND_SOC_WM_HUBS is not set
 CONFIG_SND_SOC_MXC_HDMI=y
 CONFIG_SND_SOC_MXC_SPDIF=y
 CONFIG_SND_SOC_SGTL5000=y
 CONFIG_SND_SOC_CS42888=y
 CONFIG_SND_SOC_WM8962=y
-CONFIG_SND_SOC_WM8994=y
+# CONFIG_SND_SOC_WM8994 is not set
 # CONFIG_SOUND_PRIME is not set
 CONFIG_AC97_BUS=y
 CONFIG_HID_SUPPORT=y
diff --git a/arch/arm/configs/imx6s_defconfig b/arch/arm/configs/imx6s_defconfig
index ac7afdfdf5ff..41f43e5c0d63 100644
--- a/arch/arm/configs/imx6s_defconfig
+++ b/arch/arm/configs/imx6s_defconfig
@@ -1620,7 +1620,7 @@ CONFIG_MXC_CAMERA_OV5640=y
 # CONFIG_MXC_CAMERA_OV5640_MIPI is not set
 CONFIG_MXC_CAMERA_SENSOR_CLK=y
 CONFIG_VIDEO_MXC_OUTPUT=y
-# CONFIG_VIDEO_MXC_PXP_V4L2 is not set
+CONFIG_VIDEO_MXC_PXP_V4L2=y
 # CONFIG_VIDEO_MXC_OPL is not set
 # CONFIG_VIDEO_CPIA2 is not set
 # CONFIG_VIDEO_TIMBERDALE is not set
diff --git a/arch/arm/mach-mx6/board-mx6q_arm2.c b/arch/arm/mach-mx6/board-mx6q_arm2.c
index 883ec3e5bbdb..12f87b526253 100644
--- a/arch/arm/mach-mx6/board-mx6q_arm2.c
+++ b/arch/arm/mach-mx6/board-mx6q_arm2.c
@@ -164,6 +164,7 @@ static struct clk *sata_clk;
 static int esai_record;
 static int sgtl5000_en;
 static int spdif_en;
+static int gpmi_en;
 static int flexcan_en;
 static int disable_mipi_dsi;
 
@@ -1954,6 +1955,14 @@ static int __init early_enable_spdif(char *p)
 
 early_param("spdif", early_enable_spdif);
 
+static int __init early_enable_gpmi(char *p)
+{
+	gpmi_en = 1;
+	return 0;
+}
+
+early_param("gpmi", early_enable_gpmi);
+
 static int __init early_enable_can(char *p)
 {
 	flexcan_en = 1;
@@ -2206,7 +2215,8 @@ static void __init mx6_arm2_init(void)
 	imx6q_add_viim();
 	imx6q_add_imx2_wdt(0, NULL);
 	imx6q_add_dma();
-	imx6q_add_gpmi(&mx6_gpmi_nand_platform_data);
+	if (gpmi_en)
+		imx6q_add_gpmi(&mx6_gpmi_nand_platform_data);
 
 	imx6q_add_dvfs_core(&arm2_dvfscore_data);
 
diff --git a/arch/arm/mach-mx6/board-mx6q_sabreauto.h b/arch/arm/mach-mx6/board-mx6q_sabreauto.h
index 88cb7ff7456f..fee469abfbb0 100644
--- a/arch/arm/mach-mx6/board-mx6q_sabreauto.h
+++ b/arch/arm/mach-mx6/board-mx6q_sabreauto.h
@@ -257,8 +257,6 @@ static iomux_v3_cfg_t mx6q_gpmi_nand[] __initdata = {
 	MX6Q_PAD_NANDF_ALE__RAWNAND_ALE,
 	MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N,
 	MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N,
-	MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N,
-	MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N,
 	MX6Q_PAD_NANDF_RB0__RAWNAND_READY0,
 	MX6Q_PAD_SD4_DAT0__RAWNAND_DQS,
 	MX6Q_PAD_NANDF_D0__RAWNAND_D0,
diff --git a/arch/arm/mach-mx6/board-mx6solo_sabreauto.h b/arch/arm/mach-mx6/board-mx6solo_sabreauto.h
index b752faae33ba..18f5d9062e86 100644
--- a/arch/arm/mach-mx6/board-mx6solo_sabreauto.h
+++ b/arch/arm/mach-mx6/board-mx6solo_sabreauto.h
@@ -254,8 +254,6 @@ static iomux_v3_cfg_t mx6dl_gpmi_nand[] __initdata = {
 	MX6DL_PAD_NANDF_ALE__RAWNAND_ALE,
 	MX6DL_PAD_NANDF_CS0__RAWNAND_CE0N,
 	MX6DL_PAD_NANDF_CS1__RAWNAND_CE1N,
-	MX6DL_PAD_NANDF_CS2__RAWNAND_CE2N,
-	MX6DL_PAD_NANDF_CS3__RAWNAND_CE3N,
 	MX6DL_PAD_NANDF_RB0__RAWNAND_READY0,
 	MX6DL_PAD_SD4_DAT0__RAWNAND_DQS,
 	MX6DL_PAD_NANDF_D0__RAWNAND_D0,
diff --git a/arch/arm/mach-mx6/mx6_anatop_regulator.c b/arch/arm/mach-mx6/mx6_anatop_regulator.c
index f2c2ebf600b3..9599a5439e54 100644
--- a/arch/arm/mach-mx6/mx6_anatop_regulator.c
+++ b/arch/arm/mach-mx6/mx6_anatop_regulator.c
@@ -273,6 +273,24 @@ static int is_enabled(struct anatop_regulator *sreg)
 {
 	return 1;
 }
+static int vdd3p0_enable(struct anatop_regulator *sreg)
+{
+	__raw_writel(BM_ANADIG_REG_3P0_ENABLE_LINREG,
+					sreg->rdata->control_reg+4);
+	return 0;
+}
+
+static int vdd3p0_disable(struct anatop_regulator *sreg)
+{
+	__raw_writel(BM_ANADIG_REG_3P0_ENABLE_LINREG,
+					sreg->rdata->control_reg+8);
+	return 0;
+}
+
+static int vdd3p0_is_enabled(struct anatop_regulator *sreg)
+{
+	return !!(__raw_readl(sreg->rdata->control_reg) & BM_ANADIG_REG_3P0_ENABLE_LINREG);
+}
 
 static struct anatop_regulator_data vddpu_data = {
 	.name		= "vddpu",
@@ -353,15 +371,15 @@ static struct anatop_regulator_data vdd3p0_data = {
 	.name		= "vdd3p0",
 	.set_voltage	= set_voltage,
 	.get_voltage	= get_voltage,
-	.enable		= enable,
-	.disable	= disable,
-	.is_enabled	= is_enabled,
+	.enable		= vdd3p0_enable,
+	.disable		= vdd3p0_disable,
+	.is_enabled	= vdd3p0_is_enabled,
 	.control_reg	= (u32)(MXC_PLL_BASE + HW_ANADIG_REG_3P0),
 	.vol_bit_shift	= 8,
 	.vol_bit_mask	= 0x1F,
-	.min_bit_val	= 7,
-	.min_voltage	= 2800000,
-	.max_voltage	= 3150000,
+	.min_bit_val	= 0,
+	.min_voltage	= 2625000,
+	.max_voltage	= 3400000,
 };
 
 /* CPU */
@@ -386,6 +404,13 @@ static struct regulator_consumer_supply vddsoc_consumers[] = {
 	},
 };
 
+/* USB phy 3P0 */
+static struct regulator_consumer_supply vdd3p0_consumers[] = {
+	{
+		.supply = "cpu_vdd3p0",
+	},
+};
+
 static struct regulator_init_data vddpu_init = {
 	.constraints = {
 		.name			= "vddpu",
@@ -467,16 +492,17 @@ static struct regulator_init_data vdd1p1_init = {
 static struct regulator_init_data vdd3p0_init = {
 	.constraints = {
 		.name			= "vdd3p0",
-		.min_uV			= 2800000,
-		.max_uV			= 3150000,
+		.min_uV			= 2625000,
+		.max_uV			= 3400000,
 		.valid_modes_mask	= REGULATOR_MODE_FAST |
 					  REGULATOR_MODE_NORMAL,
 		.valid_ops_mask		= REGULATOR_CHANGE_VOLTAGE |
-					  REGULATOR_CHANGE_MODE,
-		.always_on		= 1,
+					  REGULATOR_CHANGE_MODE |
+					  REGULATOR_CHANGE_STATUS,
+		.always_on		= 0,
 	},
-	.num_consumer_supplies = 0,
-	.consumer_supplies = NULL,
+	.num_consumer_supplies = ARRAY_SIZE(vdd3p0_consumers),
+	.consumer_supplies = &vdd3p0_consumers[0],
 };
 
 static struct anatop_regulator vddpu_reg = {
diff --git a/arch/arm/mach-mx6/mx6q_sabreauto_pmic_pfuze100.c b/arch/arm/mach-mx6/mx6q_sabreauto_pmic_pfuze100.c
index 8cb4ffcc78fa..3987777d56ff 100644
--- a/arch/arm/mach-mx6/mx6q_sabreauto_pmic_pfuze100.c
+++ b/arch/arm/mach-mx6/mx6q_sabreauto_pmic_pfuze100.c
@@ -24,7 +24,11 @@
 #include <linux/gpio.h>
 #include <linux/regulator/machine.h>
 #include <linux/mfd/pfuze.h>
+#include <linux/io.h>
 #include <mach/irqs.h>
+#include "crm_regs.h"
+#include "regs-anadig.h"
+#include "cpu_op-mx6.h"
 
 /*
  * Convenience conversion.
@@ -38,32 +42,21 @@
 #define PFUZE100_I2C_DEVICE_NAME  "pfuze100"
 /* 7-bit I2C bus slave address */
 #define PFUZE100_I2C_ADDR         (0x08)
-
- /*SWBST*/
-#define PFUZE100_SW1ASTANDBY    33
-#define PFUZE100_SW1ASTANDBY_STBY_VAL   (0x19)
-#define PFUZE100_SW1ASTANDBY_STBY_M     (0x3f<<0)
-#define PFUZE100_SW1BSTANDBY   40
-#define PFUZE100_SW1BSTANDBY_STBY_VAL  (0x19)
-#define PFUZE100_SW1BSTANDBY_STBY_M    (0x3f<<0)
-#define PFUZE100_SW1CSTANDBY    47
-#define PFUZE100_SW1CSTANDBY_STBY_VAL   (0x19)
-#define PFUZE100_SW1CSTANDBY_STBY_M     (0x3f<<0)
-#define PFUZE100_SW2STANDBY     54
-#define PFUZE100_SW2STANDBY_STBY_VAL    0x0
-#define PFUZE100_SW2STANDBY_STBY_M      (0x3f<<0)
-#define PFUZE100_SW3ASTANDBY    61
-#define PFUZE100_SW3ASTANDBY_STBY_VAL   0x0
-#define PFUZE100_SW3ASTANDBY_STBY_M     (0x3f<<0)
-#define PFUZE100_SW3BSTANDBY    68
-#define PFUZE100_SW3BSTANDBY_STBY_VAL   0x0
-#define PFUZE100_SW3BSTANDBY_STBY_M     (0x3f<<0)
-#define PFUZE100_SW4STANDBY     75
-#define PFUZE100_SW4STANDBY_STBY_VAL    0
-#define PFUZE100_SW4STANDBY_STBY_M      (0x3f<<0)
-#define PFUZE100_SWBSTCON1      102
-#define PFUZE100_SWBSTCON1_SWBSTMOD_VAL (0x1<<2)
-#define PFUZE100_SWBSTCON1_SWBSTMOD_M   (0x3<<2)
+#define PFUZE100_DEVICEID		(0x0)
+#define PFUZE100_REVID			(0x3)
+#define PFUZE100_SW1AMODE		(0x23)
+#define PFUZE100_SW1AVOL       32
+#define PFUZE100_SW1AVOL_VSEL_M        (0x3f<<0)
+#define PFUZE100_SW1CVOL       46
+#define PFUZE100_SW1CVOL_VSEL_M        (0x3f<<0)
+#define PFUZE100_SW1ACON		36
+#define PFUZE100_SW1ACON_SPEED_VAL	(0x1<<6)	/*default */
+#define PFUZE100_SW1ACON_SPEED_M	(0x3<<6)
+#define PFUZE100_SW1CCON		49
+#define PFUZE100_SW1CCON_SPEED_VAL	(0x1<<6)	/*default */
+#define PFUZE100_SW1CCON_SPEED_M	(0x3<<6)
+
+extern u32 arm_max_freq;
 
 static struct regulator_consumer_supply sw1a_consumers[] = {
 	{
@@ -157,7 +150,13 @@ static struct regulator_init_data sw1a_init = {
 			.valid_modes_mask = 0,
 			.boot_on = 1,
 			.always_on = 1,
+			.initial_state = PM_SUSPEND_MEM,
+			.state_mem = {
+				.uV = 975000,/*0.9V+6%*/
+				.mode = REGULATOR_MODE_NORMAL,
+				.enabled = 1,
 			},
+	},
 	.num_consumer_supplies = ARRAY_SIZE(sw1a_consumers),
 	.consumer_supplies = sw1a_consumers,
 };
@@ -183,7 +182,13 @@ static struct regulator_init_data sw1c_init = {
 			.valid_modes_mask = 0,
 			.always_on = 1,
 			.boot_on = 1,
+			.initial_state = PM_SUSPEND_MEM,
+			.state_mem = {
+				.uV = 975000,/*0.9V+6%*/
+				.mode = REGULATOR_MODE_NORMAL,
+				.enabled = 1,
 			},
+	},
 	.num_consumer_supplies = ARRAY_SIZE(sw1c_consumers),
 	.consumer_supplies = sw1c_consumers,
 };
@@ -391,20 +396,82 @@ static struct regulator_init_data vgen6_init = {
 
 static int pfuze100_init(struct mc_pfuze *pfuze)
 {
-	int ret;
-	ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ASTANDBY,
-			    PFUZE100_SW1ASTANDBY_STBY_M,
-			    PFUZE100_SW1ASTANDBY_STBY_VAL);
+	int ret, i;
+	unsigned int reg;
+	unsigned char value;
+	/*read Device ID*/
+	ret = pfuze_reg_read(pfuze, PFUZE100_DEVICEID, &value);
+	if (ret)
+		goto err;
+	if (value != 0x10) {
+		printk(KERN_ERR "wrong device id:%x!\n", value);
+		goto err;
+	}
+
+	/*read Revision ID*/
+	ret = pfuze_reg_read(pfuze, PFUZE100_REVID, &value);
 	if (ret)
 		goto err;
-	ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1BSTANDBY,
-			    PFUZE100_SW1BSTANDBY_STBY_M,
-			    PFUZE100_SW1BSTANDBY_STBY_VAL);
+	if (value == 0x10) {
+		printk(KERN_WARNING "PF100 1.0 chip found!\n");
+	/* workaround ER1 of pfuze1.0: set all buck regulators in PWM mode
+	* except SW1C(APS) in normal and  PFM mode in standby.
+	*/
+		for (i = 0; i < 7; i++) {
+			if (i == 2)/*SW1C*/
+				value = 0xc;/*normal:APS mode;standby:PFM mode*/
+			else
+				value = 0xd;/*normal:PWM mode;standby:PFM mode*/
+			ret = pfuze_reg_write(pfuze,
+					PFUZE100_SW1AMODE + (i * 7),
+					value);
+			if (ret)
+				goto err;
+		}
+
+	} else {
+	/*set all switches APS in normal and PFM mode in standby*/
+		for (i = 0; i < 7; i++) {
+			value = 0xc;
+			ret = pfuze_reg_write(pfuze,
+					PFUZE100_SW1AMODE + (i * 7),
+					value);
+			if (ret)
+				goto err;
+		}
+
+	}
+	if (arm_max_freq == CPU_AT_1_2GHz) {
+		/*VDDARM_IN 1.475V*/
+		ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1AVOL,
+					PFUZE100_SW1AVOL_VSEL_M,
+					0x2f);
+		if (ret)
+			goto err;
+		/*VDDSOC_IN 1.475V*/
+		ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CVOL,
+					PFUZE100_SW1CVOL_VSEL_M,
+					0x2f);
+		if (ret)
+			goto err;
+		/*set VDDSOC&VDDPU to 1.25V*/
+		reg = __raw_readl(ANADIG_REG_CORE);
+		reg &= ~BM_ANADIG_REG_CORE_REG2_TRG;
+		reg |= BF_ANADIG_REG_CORE_REG2_TRG(0x16);
+		reg &= ~BM_ANADIG_REG_CORE_REG1_TRG;
+		reg |= BF_ANADIG_REG_CORE_REG1_TRG(0x16);
+		__raw_writel(reg, ANADIG_REG_CORE);
+
+	}
+	/*set SW1AB/1C DVSPEED as 25mV step each 4us,quick than 16us before.*/
+	ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ACON,
+			    PFUZE100_SW1ACON_SPEED_M,
+			    PFUZE100_SW1ACON_SPEED_VAL);
 	if (ret)
 		goto err;
-	ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CSTANDBY,
-			    PFUZE100_SW1CSTANDBY_STBY_M,
-			    PFUZE100_SW1CSTANDBY_STBY_VAL);
+	ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CCON,
+			    PFUZE100_SW1CCON_SPEED_M,
+			    PFUZE100_SW1CCON_SPEED_VAL);
 	if (ret)
 		goto err;
 	return 0;
diff --git a/arch/arm/mach-mx6/mx6q_sabresd_pmic_pfuze100.c b/arch/arm/mach-mx6/mx6q_sabresd_pmic_pfuze100.c
index cbde44955f03..6b38bd000bc0 100644
--- a/arch/arm/mach-mx6/mx6q_sabresd_pmic_pfuze100.c
+++ b/arch/arm/mach-mx6/mx6q_sabresd_pmic_pfuze100.c
@@ -41,36 +41,14 @@
 
 #define PFUZE100_I2C_DEVICE_NAME  "pfuze100"
 /* 7-bit I2C bus slave address */
-#define PFUZE100_I2C_ADDR         (0x08)
- /*SWBST*/
-#define PFUZE100_SW1AVOL	32
-#define PFUZE100_SW1AVOL_VSEL_M	(0x3f<<0)
-#define PFUZE100_SW1CVOL	46
-#define PFUZE100_SW1CVOL_VSEL_M	(0x3f<<0)
-#define PFUZE100_SW1ASTANDBY	33
-#define PFUZE100_SW1ASTANDBY_STBY_VAL	(0x19)
-#define PFUZE100_SW1ASTANDBY_STBY_M	(0x3f<<0)
-#define PFUZE100_SW1BSTANDBY   40
-#define PFUZE100_SW1BSTANDBY_STBY_VAL  (0x19)
-#define PFUZE100_SW1BSTANDBY_STBY_M    (0x3f<<0)
-#define PFUZE100_SW1CSTANDBY	47
-#define PFUZE100_SW1CSTANDBY_STBY_VAL	(0x19)
-#define PFUZE100_SW1CSTANDBY_STBY_M	(0x3f<<0)
-#define PFUZE100_SW2STANDBY     54
-#define PFUZE100_SW2STANDBY_STBY_VAL    0x0
-#define PFUZE100_SW2STANDBY_STBY_M      (0x3f<<0)
-#define PFUZE100_SW3ASTANDBY    61
-#define PFUZE100_SW3ASTANDBY_STBY_VAL   0x0
-#define PFUZE100_SW3ASTANDBY_STBY_M     (0x3f<<0)
-#define PFUZE100_SW3BSTANDBY    68
-#define PFUZE100_SW3BSTANDBY_STBY_VAL   0x0
-#define PFUZE100_SW3BSTANDBY_STBY_M     (0x3f<<0)
-#define PFUZE100_SW4STANDBY     75
-#define PFUZE100_SW4STANDBY_STBY_VAL    0
-#define PFUZE100_SW4STANDBY_STBY_M      (0x3f<<0)
-#define PFUZE100_SWBSTCON1	102
-#define PFUZE100_SWBSTCON1_SWBSTMOD_VAL	(0x1<<2)
-#define PFUZE100_SWBSTCON1_SWBSTMOD_M	(0x3<<2)
+#define PFUZE100_I2C_ADDR		(0x08)
+#define PFUZE100_DEVICEID		(0x0)
+#define PFUZE100_REVID			(0x3)
+#define PFUZE100_SW1AMODE		(0x23)
+#define PFUZE100_SW1AVOL       32
+#define PFUZE100_SW1AVOL_VSEL_M        (0x3f<<0)
+#define PFUZE100_SW1CVOL       46
+#define PFUZE100_SW1CVOL_VSEL_M        (0x3f<<0)
 #define PFUZE100_SW1ACON		36
 #define PFUZE100_SW1ACON_SPEED_VAL	(0x1<<6)	/*default */
 #define PFUZE100_SW1ACON_SPEED_M	(0x3<<6)
@@ -166,7 +144,13 @@ static struct regulator_init_data sw1a_init = {
 			.valid_modes_mask = 0,
 			.boot_on = 1,
 			.always_on = 1,
+			.initial_state = PM_SUSPEND_MEM,
+			.state_mem = {
+				.uV = 975000,/*0.9V+6%*/
+				.mode = REGULATOR_MODE_NORMAL,
+				.enabled = 1,
 			},
+	},
 
 #ifdef CONFIG_MX6_INTER_LDO_BYPASS
 	.num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
@@ -195,7 +179,13 @@ static struct regulator_init_data sw1c_init = {
 			.valid_modes_mask = 0,
 			.always_on = 1,
 			.boot_on = 1,
+			.initial_state = PM_SUSPEND_MEM,
+			.state_mem = {
+				.uV = 975000,/*0.9V+6%*/
+				.mode = REGULATOR_MODE_NORMAL,
+				.enabled = 1,
 			},
+	},
 #ifdef CONFIG_MX6_INTER_LDO_BYPASS
 	.num_consumer_supplies = ARRAY_SIZE(sw1c_consumers),
 	.consumer_supplies = sw1c_consumers,
@@ -399,8 +389,52 @@ static struct regulator_init_data vgen6_init = {
 
 static int pfuze100_init(struct mc_pfuze *pfuze)
 {
-	int ret;
+	int ret, i;
 	unsigned int reg;
+	unsigned char value;
+	/*read Device ID*/
+	ret = pfuze_reg_read(pfuze, PFUZE100_DEVICEID, &value);
+	if (ret)
+		goto err;
+	if (value != 0x10) {
+		printk(KERN_ERR "wrong device id:%x!\n", value);
+		goto err;
+	}
+
+	/*read Revision ID*/
+	ret = pfuze_reg_read(pfuze, PFUZE100_REVID, &value);
+	if (ret)
+		goto err;
+	if (value == 0x10) {
+		printk(KERN_WARNING "PF100 1.0 chip found!\n");
+	/* workaround ER1 of pfuze1.0: set all buck regulators in PWM mode
+	* except SW1C(APS) in normal and  PFM mode in standby.
+	*/
+		for (i = 0; i < 7; i++) {
+			if (i == 2)/*SW1C*/
+				value = 0xc;/*normal:APS mode;standby:PFM mode*/
+			else
+				value = 0xd;/*normal:PWM mode;standby:PFM mode*/
+			ret = pfuze_reg_write(pfuze,
+					PFUZE100_SW1AMODE + (i * 7),
+					value);
+			if (ret)
+				goto err;
+		}
+
+	} else {
+	/*set all switches APS in normal and PFM mode in standby*/
+		for (i = 0; i < 7; i++) {
+			value = 0xc;
+			ret = pfuze_reg_write(pfuze,
+					PFUZE100_SW1AMODE + (i * 7),
+					value);
+			if (ret)
+				goto err;
+		}
+
+	}
+
 	if (arm_max_freq == CPU_AT_1_2GHz) {
 		/*VDDARM_IN 1.475V*/
 		ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1AVOL,
@@ -423,16 +457,6 @@ static int pfuze100_init(struct mc_pfuze *pfuze)
 		__raw_writel(reg, ANADIG_REG_CORE);
 
 	}
-	ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ASTANDBY,
-			    PFUZE100_SW1ASTANDBY_STBY_M,
-			    PFUZE100_SW1ASTANDBY_STBY_VAL);
-	if (ret)
-		goto err;
-	ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CSTANDBY,
-			    PFUZE100_SW1CSTANDBY_STBY_M,
-			    PFUZE100_SW1CSTANDBY_STBY_VAL);
-	if (ret)
-		goto err;
 	/*set SW1AB/1C DVSPEED as 25mV step each 4us,quick than 16us before.*/
 	ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ACON,
 			    PFUZE100_SW1ACON_SPEED_M,
diff --git a/arch/arm/mach-mx6/mx6sl_arm2_pmic_pfuze100.c b/arch/arm/mach-mx6/mx6sl_arm2_pmic_pfuze100.c
index 5cf34073bdc1..55a802b76b68 100644
--- a/arch/arm/mach-mx6/mx6sl_arm2_pmic_pfuze100.c
+++ b/arch/arm/mach-mx6/mx6sl_arm2_pmic_pfuze100.c
@@ -38,31 +38,9 @@
 #define PFUZE100_I2C_DEVICE_NAME  "pfuze100"
 /* 7-bit I2C bus slave address */
 #define PFUZE100_I2C_ADDR         (0x08)
- /*SWBST*/
-#define PFUZE100_SW1ASTANDBY	33
-#define PFUZE100_SW1ASTANDBY_STBY_VAL	(0x19)	/* 925mV */
-#define PFUZE100_SW1ASTANDBY_STBY_M	(0x3f<<0)
-#define PFUZE100_SW1BSTANDBY   40
-#define PFUZE100_SW1BSTANDBY_STBY_VAL  (0x19)	/* 925mV */
-#define PFUZE100_SW1BSTANDBY_STBY_M    (0x3f<<0)
-#define PFUZE100_SW1CSTANDBY	47
-#define PFUZE100_SW1CSTANDBY_STBY_VAL	(0x19)	/* 925mV */
-#define PFUZE100_SW1CSTANDBY_STBY_M	(0x3f<<0)
-#define PFUZE100_SW2STANDBY     54
-#define PFUZE100_SW2STANDBY_STBY_VAL    0x0
-#define PFUZE100_SW2STANDBY_STBY_M      (0x3f<<0)
-#define PFUZE100_SW3ASTANDBY    61
-#define PFUZE100_SW3ASTANDBY_STBY_VAL   0x0
-#define PFUZE100_SW3ASTANDBY_STBY_M     (0x3f<<0)
-#define PFUZE100_SW3BSTANDBY    68
-#define PFUZE100_SW3BSTANDBY_STBY_VAL   0x0
-#define PFUZE100_SW3BSTANDBY_STBY_M     (0x3f<<0)
-#define PFUZE100_SW4STANDBY     75
-#define PFUZE100_SW4STANDBY_STBY_VAL    0
-#define PFUZE100_SW4STANDBY_STBY_M      (0x3f<<0)
-#define PFUZE100_SWBSTCON1	102
-#define PFUZE100_SWBSTCON1_SWBSTMOD_VAL	(0x1<<2)
-#define PFUZE100_SWBSTCON1_SWBSTMOD_M	(0x3<<2)
+#define PFUZE100_DEVICEID		(0x0)
+#define PFUZE100_REVID			(0x3)
+#define PFUZE100_SW1AMODE		(0x23)
 #define PFUZE100_SW1ACON		36
 #define PFUZE100_SW1ACON_SPEED_VAL	(0x1<<6)	/*default */
 #define PFUZE100_SW1ACON_SPEED_M	(0x3<<6)
@@ -158,7 +136,13 @@ static struct regulator_init_data sw1a_init = {
 			.valid_modes_mask = 0,
 			.boot_on = 1,
 			.always_on = 1,
+			.initial_state = PM_SUSPEND_MEM,
+			.state_mem = {
+				.uV = 975000,/*0.9V+6%*/
+				.mode = REGULATOR_MODE_NORMAL,
+				.enabled = 1,
 			},
+	},
 #ifdef CONFIG_MX6_INTER_LDO_BYPASS
 	.num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
 	.consumer_supplies = sw1_consumers,
@@ -186,7 +170,13 @@ static struct regulator_init_data sw1c_init = {
 			.valid_modes_mask = 0,
 			.always_on = 1,
 			.boot_on = 1,
+			.initial_state = PM_SUSPEND_MEM,
+			.state_mem = {
+				.uV = 975000,/*0.9V+6%*/
+				.mode = REGULATOR_MODE_NORMAL,
+				.enabled = 1,
 			},
+	},
 	#ifdef CONFIG_MX6_INTER_LDO_BYPASS
 	.num_consumer_supplies = ARRAY_SIZE(sw1c_consumers),
 	.consumer_supplies = sw1c_consumers,
@@ -392,17 +382,51 @@ static struct regulator_init_data vgen6_init = {
 
 static int pfuze100_init(struct mc_pfuze *pfuze)
 {
-	int ret;
-	ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ASTANDBY,
-			    PFUZE100_SW1ASTANDBY_STBY_M,
-			    PFUZE100_SW1ASTANDBY_STBY_VAL);
+	int ret, i;
+	unsigned int reg;
+	unsigned char value;
+	/*read Device ID*/
+	ret = pfuze_reg_read(pfuze, PFUZE100_DEVICEID, &value);
 	if (ret)
 		goto err;
-	ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CSTANDBY,
-			    PFUZE100_SW1CSTANDBY_STBY_M,
-			    PFUZE100_SW1CSTANDBY_STBY_VAL);
+	if (value != 0x10) {
+		printk(KERN_ERR "wrong device id:%x!\n", value);
+		goto err;
+	}
+
+	/*read Revision ID*/
+	ret = pfuze_reg_read(pfuze, PFUZE100_REVID, &value);
 	if (ret)
 		goto err;
+	if (value == 0x10) {
+		printk(KERN_WARNING "PF100 1.0 chip found!\n");
+	/* workaround ER1 of pfuze1.0: set all buck regulators in PWM mode
+	* except SW1C(APS) in normal and  PFM mode in standby.
+	*/
+		for (i = 0; i < 7; i++) {
+			if (i == 2)/*SW1C*/
+				value = 0xc;/*normal:APS mode;standby:PFM mode*/
+			else
+				value = 0xd;/*normal:PWM mode;standby:PFM mode*/
+			ret = pfuze_reg_write(pfuze,
+					PFUZE100_SW1AMODE + (i * 7),
+					value);
+			if (ret)
+				goto err;
+		}
+
+	} else {
+	/*set all switches APS in normal and PFM mode in standby*/
+		for (i = 0; i < 7; i++) {
+			value = 0xc;
+			ret = pfuze_reg_write(pfuze,
+					PFUZE100_SW1AMODE + (i * 7),
+					value);
+			if (ret)
+				goto err;
+		}
+
+	}
 	/*set SW1AB/SW1C DVSPEED as 25mV step each 4us,quick than 16us before.*/
 	ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ACON,
 			    PFUZE100_SW1ACON_SPEED_M,
diff --git a/arch/arm/mach-mx6/mx6sl_evk_pmic_pfuze100.c b/arch/arm/mach-mx6/mx6sl_evk_pmic_pfuze100.c
index 981d149d7aee..bfd5fafc1d1b 100644
--- a/arch/arm/mach-mx6/mx6sl_evk_pmic_pfuze100.c
+++ b/arch/arm/mach-mx6/mx6sl_evk_pmic_pfuze100.c
@@ -38,31 +38,9 @@
 #define PFUZE100_I2C_DEVICE_NAME  "pfuze100"
 /* 7-bit I2C bus slave address */
 #define PFUZE100_I2C_ADDR         (0x08)
- /*SWBST*/
-#define PFUZE100_SW1ASTANDBY	33
-#define PFUZE100_SW1ASTANDBY_STBY_VAL	(0x19)	/* 925mv */
-#define PFUZE100_SW1ASTANDBY_STBY_M	(0x3f<<0)
-#define PFUZE100_SW1BSTANDBY   40
-#define PFUZE100_SW1BSTANDBY_STBY_VAL  (0x19)	/* 925mv */
-#define PFUZE100_SW1BSTANDBY_STBY_M    (0x3f<<0)
-#define PFUZE100_SW1CSTANDBY	47
-#define PFUZE100_SW1CSTANDBY_STBY_VAL	(0x19)	/* 925mv */
-#define PFUZE100_SW1CSTANDBY_STBY_M	(0x3f<<0)
-#define PFUZE100_SW2STANDBY     54
-#define PFUZE100_SW2STANDBY_STBY_VAL    0x0
-#define PFUZE100_SW2STANDBY_STBY_M      (0x3f<<0)
-#define PFUZE100_SW3ASTANDBY    61
-#define PFUZE100_SW3ASTANDBY_STBY_VAL   0x0
-#define PFUZE100_SW3ASTANDBY_STBY_M     (0x3f<<0)
-#define PFUZE100_SW3BSTANDBY    68
-#define PFUZE100_SW3BSTANDBY_STBY_VAL   0x0
-#define PFUZE100_SW3BSTANDBY_STBY_M     (0x3f<<0)
-#define PFUZE100_SW4STANDBY     75
-#define PFUZE100_SW4STANDBY_STBY_VAL    0
-#define PFUZE100_SW4STANDBY_STBY_M      (0x3f<<0)
-#define PFUZE100_SWBSTCON1	102
-#define PFUZE100_SWBSTCON1_SWBSTMOD_VAL	(0x1<<2)
-#define PFUZE100_SWBSTCON1_SWBSTMOD_M	(0x3<<2)
+#define PFUZE100_DEVICEID		(0x0)
+#define PFUZE100_REVID			(0x3)
+#define PFUZE100_SW1AMODE		(0x23)
 #define PFUZE100_SW1ACON		36
 #define PFUZE100_SW1ACON_SPEED_VAL	(0x1<<6)	/*default */
 #define PFUZE100_SW1ACON_SPEED_M	(0x3<<6)
@@ -161,7 +139,13 @@ static struct regulator_init_data sw1a_init = {
 			.valid_modes_mask = 0,
 			.boot_on = 1,
 			.always_on = 1,
+			.initial_state = PM_SUSPEND_MEM,
+			.state_mem = {
+				.uV = 975000,/*0.9V+6%*/
+				.mode = REGULATOR_MODE_NORMAL,
+				.enabled = 1,
 			},
+	},
 #ifdef CONFIG_MX6_INTER_LDO_BYPASS
 	.num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
 	.consumer_supplies = sw1_consumers,
@@ -189,7 +173,13 @@ static struct regulator_init_data sw1c_init = {
 			.valid_modes_mask = 0,
 			.always_on = 1,
 			.boot_on = 1,
+			.initial_state = PM_SUSPEND_MEM,
+			.state_mem = {
+				.uV = 975000,/*0.9V+6%*/
+				.mode = REGULATOR_MODE_NORMAL,
+				.enabled = 1,
 			},
+	},
 #ifdef CONFIG_MX6_INTER_LDO_BYPASS
 	.num_consumer_supplies = ARRAY_SIZE(sw1c_consumers),
 	.consumer_supplies = sw1c_consumers,
@@ -397,17 +387,52 @@ static struct regulator_init_data vgen6_init = {
 
 static int pfuze100_init(struct mc_pfuze *pfuze)
 {
-	int ret;
-	ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ASTANDBY,
-			    PFUZE100_SW1ASTANDBY_STBY_M,
-			    PFUZE100_SW1ASTANDBY_STBY_VAL);
+	int ret, i;
+	unsigned int reg;
+	unsigned char value;
+	/*read Device ID*/
+	ret = pfuze_reg_read(pfuze, PFUZE100_DEVICEID, &value);
 	if (ret)
 		goto err;
-	ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CSTANDBY,
-			    PFUZE100_SW1CSTANDBY_STBY_M,
-			    PFUZE100_SW1CSTANDBY_STBY_VAL);
+	if (value != 0x10) {
+		printk(KERN_ERR "wrong device id:%x!\n", value);
+		goto err;
+	}
+
+	/*read Revision ID*/
+	ret = pfuze_reg_read(pfuze, PFUZE100_REVID, &value);
 	if (ret)
 		goto err;
+	if (value == 0x10) {
+		printk(KERN_WARNING "PF100 1.0 chip found!\n");
+	/* workaround ER1 of pfuze1.0: set all buck regulators in PWM mode
+	* except SW1C(APS) in normal and  PFM mode in standby.
+	*/
+		for (i = 0; i < 7; i++) {
+			if (i == 2)/*SW1C*/
+				value = 0xc;/*normal:APS mode;standby:PFM mode*/
+			else
+				value = 0xd;/*normal:PWM mode;standby:PFM mode*/
+			ret = pfuze_reg_write(pfuze,
+					PFUZE100_SW1AMODE + (i * 7),
+					value);
+			if (ret)
+				goto err;
+		}
+
+	} else {
+	/*set all switches APS in normal and PFM mode in standby*/
+		for (i = 0; i < 7; i++) {
+			value = 0xc;
+			ret = pfuze_reg_write(pfuze,
+					PFUZE100_SW1AMODE + (i * 7),
+					value);
+			if (ret)
+				goto err;
+		}
+
+	}
+
 	/*set SW1AB/SW1CDVSPEED as 25mV step each 4us,quick than 16us before.*/
 	ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ACON,
 			    PFUZE100_SW1ACON_SPEED_M,
diff --git a/arch/arm/mach-mx6/pm.c b/arch/arm/mach-mx6/pm.c
index b29c6f6ab0d3..18b8de8a8e87 100644
--- a/arch/arm/mach-mx6/pm.c
+++ b/arch/arm/mach-mx6/pm.c
@@ -68,11 +68,13 @@
 #define LOCAL_TWD_INT_OFFSET		0xc
 #define ANATOP_REG_2P5_OFFSET		0x130
 #define ANATOP_REG_CORE_OFFSET		0x140
+#define VDD3P0_VOLTAGE                   3200000
 
 static struct clk *cpu_clk;
 static struct clk *axi_clk;
 static struct clk *periph_clk;
 static struct clk *pll3_usb_otg_main_clk;
+static struct regulator *vdd3p0_regulator;
 
 static struct pm_platform_data *pm_data;
 
@@ -178,6 +180,8 @@ static void usb_power_up_handler(void)
 
 static void disp_power_down(void)
 {
+#if !defined(CONFIG_FB_MXC_ELCDIF_FB) && \
+    !defined(CONFIG_FB_MXC_ELCDIF_FB_MODULE)
 	if (cpu_is_mx6sl()) {
 		__raw_writel(0xFFFFFFFF, gpc_base + GPC_PGC_DISP_PUPSCR_OFFSET);
 		__raw_writel(0xFFFFFFFF, gpc_base + GPC_PGC_DISP_PDNSCR_OFFSET);
@@ -194,10 +198,13 @@ static void disp_power_down(void)
 			~MXC_CCM_CCGRx_CG1_MASK, MXC_CCM_CCGR3);
 
 	}
+#endif
 }
 
 static void disp_power_up(void)
 {
+#if !defined(CONFIG_FB_MXC_ELCDIF_FB) && \
+    !defined(CONFIG_FB_MXC_ELCDIF_FB_MODULE)
 	if (cpu_is_mx6sl()) {
 		/*
 		 * Need to enable EPDC/LCDIF pix clock, and
@@ -214,6 +221,7 @@ static void disp_power_up(void)
 		__raw_writel(0x20, gpc_base + GPC_CNTR_OFFSET);
 		__raw_writel(0x1, gpc_base + GPC_PGC_DISP_SR_OFFSET);
 	}
+#endif
 }
 
 static void mx6_suspend_store(void)
@@ -404,7 +412,12 @@ static int mx6_suspend_enter(suspend_state_t state)
  */
 static int mx6_suspend_prepare(void)
 {
-
+	int ret;
+	ret = regulator_disable(vdd3p0_regulator);
+	if (ret) {
+		printk(KERN_ERR "%s: failed to disable 3p0 regulator Err: %d\n",
+							__func__, ret);
+	}
 	return 0;
 }
 
@@ -413,6 +426,12 @@ static int mx6_suspend_prepare(void)
  */
 static void mx6_suspend_finish(void)
 {
+	int ret;
+	ret = regulator_enable(vdd3p0_regulator);
+	if (ret) {
+		printk(KERN_ERR "%s: failed to enable 3p0 regulator Err: %d\n",
+						__func__, ret);
+	}
 }
 
 #ifdef CONFIG_MX6_INTER_LDO_BYPASS
@@ -466,6 +485,7 @@ static struct platform_driver mx6_pm_driver = {
 
 static int __init pm_init(void)
 {
+	int ret = 0;
 	scu_base = IO_ADDRESS(SCU_BASE_ADDR);
 	gpc_base = IO_ADDRESS(GPC_BASE_ADDR);
 	src_base = IO_ADDRESS(SRC_BASE_ADDR);
@@ -523,6 +543,24 @@ static int __init pm_init(void)
 		return PTR_ERR(pll3_usb_otg_main_clk);
 	}
 
+	vdd3p0_regulator = regulator_get(NULL, "cpu_vdd3p0");
+	if (IS_ERR(vdd3p0_regulator)) {
+		printk(KERN_ERR "%s: failed to get 3p0 regulator Err: %d\n",
+						__func__, ret);
+		return PTR_ERR(vdd3p0_regulator);
+	}
+	ret = regulator_set_voltage(vdd3p0_regulator, VDD3P0_VOLTAGE,
+							VDD3P0_VOLTAGE);
+	if (ret) {
+		printk(KERN_ERR "%s: failed to set 3p0 regulator voltage Err: %d\n",
+						__func__, ret);
+	}
+	ret = regulator_enable(vdd3p0_regulator);
+	if (ret) {
+		printk(KERN_ERR "%s: failed to enable 3p0 regulator Err: %d\n",
+						__func__, ret);
+	}
+
 	printk(KERN_INFO "PM driver module loaded\n");
 
 	return 0;
@@ -532,6 +570,7 @@ static void __exit pm_cleanup(void)
 {
 	/* Unregister the device structure */
 	platform_driver_unregister(&mx6_pm_driver);
+	regulator_put(vdd3p0_regulator);
 }
 
 module_init(pm_init);
diff --git a/arch/arm/plat-mxc/include/mach/mxc_vpu.h b/arch/arm/plat-mxc/include/mach/mxc_vpu.h
index 0c0fa2aad38b..7a6e24f2b0dd 100755
--- a/arch/arm/plat-mxc/include/mach/mxc_vpu.h
+++ b/arch/arm/plat-mxc/include/mach/mxc_vpu.h
@@ -67,6 +67,7 @@ struct vpu_mem_desc {
 #define BIT_INT_REASON			0x174
 
 #define MJPEG_PIC_STATUS_REG		0x3004
+#define MBC_SET_SUBBLK_EN		0x4A0
 
 #define BIT_WORK_CTRL_BUF_BASE		0x100
 #define BIT_WORK_CTRL_BUF_REG(i)	(BIT_WORK_CTRL_BUF_BASE + i * 4)
@@ -77,7 +78,11 @@ struct vpu_mem_desc {
 #define BIT_FRAME_MEM_CTRL		BIT_WORK_CTRL_BUF_REG(4)
 #define BIT_BIT_STREAM_PARAM		BIT_WORK_CTRL_BUF_REG(5)
 
+#ifndef CONFIG_ARCH_MX6
 #define BIT_RESET_CTRL			0x11C
+#else
+#define BIT_RESET_CTRL			0x128
+#endif
 
 /* i could be 0, 1, 2, 3 */
 #define	BIT_RD_PTR_BASE			0x120