diff options
| author | Juha Tukkinen <jtukkinen@nvidia.com> | 2012-04-11 16:47:29 +0300 |
|---|---|---|
| committer | Rohan Somvanshi <rsomvanshi@nvidia.com> | 2012-04-19 04:54:06 -0700 |
| commit | 20395e4c50ceea0d114c9beaaa5fa0e18b87915e (patch) | |
| tree | b9805bfeaf9be5aeb7e6aeb1f8d37061c618d077 /arch | |
| parent | 8059ef65ae2efe2535301b9b26636c9fe6b4954e (diff) | |
ARM: tegra: remove T30 FPGA support
Remove T30 FPGA support as it will conflict with downstreaming mainline
way of using chipid and revision.
Change-Id: Ic1fd1107801de13c265c7dde8571e0537c43f4fd
Signed-off-by: Juha Tukkinen <jtukkinen@nvidia.com>
Reviewed-on: http://git-master/r/95872
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-tegra/fuse.c | 13 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/tegra3_clocks.c | 5 |
2 files changed, 0 insertions, 18 deletions
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c index 0658ae0fe6ef..b07d222d48e8 100644 --- a/arch/arm/mach-tegra/fuse.c +++ b/arch/arm/mach-tegra/fuse.c @@ -343,19 +343,6 @@ static enum tegra_revision tegra_decode_revision(const struct tegra_id *id) revision = tegra_chip_revisions[i].revision; break; } - -#elif defined(CONFIG_TEGRA_FPGA_PLATFORM) - if ((id->chipid & 0xf0) == TEGRA_CHIPID_TEGRA3) { - if ((id->major == 0) && (id->minor == 1)) { - unsigned int patch = id->patch & 0xF; - if ((id->netlist == 12) && (patch == 12)) - revision = TEGRA_REVISION_A01; - else if ((id->netlist == 12) && (patch > 12)) - revision = TEGRA_REVISION_A02; - else if (id->netlist > 12) - revision = TEGRA_REVISION_A02; - } - } #endif return revision; diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c index d5e101ec3502..b6fb8e5334a9 100644 --- a/arch/arm/mach-tegra/tegra3_clocks.c +++ b/arch/arm/mach-tegra/tegra3_clocks.c @@ -830,10 +830,6 @@ static int tegra3_cpu_clk_set_rate(struct clk *c, unsigned long rate) bool skip_to_backup = skip && (clk_get_rate_all_locked(c) >= SKIPPER_ENGAGE_RATE); - /* Hardware clock control is not possible on FPGA platforms. - Report success so that upper level layers don't complain - needlessly. */ -#ifndef CONFIG_TEGRA_FPGA_PLATFORM if (c->dvfs) { if (!c->dvfs->dvfs_rail) return -ENOSYS; @@ -912,7 +908,6 @@ out: tegra3_super_clk_skipper_update(c->parent, 2, 1); } clk_disable(c->u.cpu.main); -#endif return ret; } |