diff options
| author | Mohit Kataria <mkataria@nvidia.com> | 2012-04-24 13:03:54 +0530 |
|---|---|---|
| committer | Simone Willett <swillett@nvidia.com> | 2012-05-25 14:34:22 -0700 |
| commit | 5f965f2c63d3e9c6b335d1f6337c83c1f5437739 (patch) | |
| tree | 845ba1fc2c30f2200198aad2c9c06a0960f9da8f /arch | |
| parent | a5b582a0ad0cd078b059c68036406f9b7f1645ce (diff) | |
Arm: Tegra3: clocks: Disabled SSCCENTER bit for plle
Disabled SSCCENTRE bit for plle as per golden register
(value provided by syseng)
Bug 942384 978870
Change-Id: I3c2f8e8e220015b58f0c8bcbaac4e9998a5b6dcd
Reviewed-on: http://git-master/r/98381
Signed-off-by: Mohit Kataria <mkataria@nvidia.com>
Reviewed-on: http://git-master/r/102408
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-tegra/tegra3_clocks.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c index 9e4e117cc3bc..9ff183377c2d 100644 --- a/arch/arm/mach-tegra/tegra3_clocks.c +++ b/arch/arm/mach-tegra/tegra3_clocks.c @@ -284,7 +284,7 @@ #define PLLE_SS_COEFFICIENTS_12MHZ \ ((0x18<<PLLE_SS_INCINTRV_SHIFT) | (0x1<<PLLE_SS_INC_SHIFT) | \ (0x24<<PLLE_SS_MAX_SHIFT)) -#define PLLE_SS_DISABLE ((1<<12) | (1<<11) | (1<<10)) +#define PLLE_SS_DISABLE ((1<<14) | (1<<12) | (1<<11) | (1<<10)) #define PLLE_AUX 0x48c #define PLLE_AUX_PLLP_SEL (1<<2) |