diff options
| author | krishna kishore <kthota@nvidia.com> | 2012-08-02 18:10:08 +0530 |
|---|---|---|
| committer | Simone Willett <swillett@nvidia.com> | 2012-08-22 12:02:04 -0700 |
| commit | 71824364492283119d1a18dd179718f85ec810c2 (patch) | |
| tree | be57b6b86faa1e8a885c73b111003e3339e8cea2 /arch | |
| parent | 7275366c68e427cb808d0a3aca27fcfe66bf8f3f (diff) | |
arch: arm: pcie: init TXBA registers
Setting default values in TXBA registers to avoid
unfair arbitration between downstream reads and
completions to upstream reads
Bug 1027024
Change-Id: I87763817b7974127f93fa18270b5245a54fc6676
Signed-off-by: krishna kishore <kthota@nvidia.com>
Reviewed-on: http://git-master/r/120359
Tested-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-tegra/pcie.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c index c6f0e4bf2bb8..eef215b00018 100644 --- a/arch/arm/mach-tegra/pcie.c +++ b/arch/arm/mach-tegra/pcie.c @@ -155,6 +155,12 @@ #define RP_VEND_XP 0x00000F00 #define RP_VEND_XP_DL_UP (1 << 30) +#define RP_TXBA1 0x00000E1C +#define RP_TXBA1_CM_OVER_PW_BURST_MASK (0xF << 4) +#define RP_TXBA1_CM_OVER_PW_BURST_INIT_VAL (0x4 << 4) +#define RP_TXBA1_PW_OVER_CM_BURST_MASK (0xF) +#define RP_TXBA1_PW_OVER_CM_BURST_INIT_VAL (0x4) + #define RP_LINK_CONTROL_STATUS 0x00000090 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000 @@ -1223,6 +1229,7 @@ static void tegra_pcie_enable_aspm_l1_support(int index) static void tegra_pcie_add_port(int index, u32 offset, u32 reset_reg) { struct tegra_pcie_port *pp; + unsigned int data; pp = tegra_pcie.port + tegra_pcie.num_ports; @@ -1237,6 +1244,18 @@ static void tegra_pcie_add_port(int index, u32 offset, u32 reset_reg) } tegra_pcie_enable_clock_clamp(index); tegra_pcie_enable_aspm_l1_support(index); + + /* + * Initialize TXBA1 register to fix the unfair arbitration + * between downstream reads and completions to upstream reads + */ + data = rp_readl(RP_TXBA1, index); + data &= ~(RP_TXBA1_PW_OVER_CM_BURST_MASK); + data |= RP_TXBA1_PW_OVER_CM_BURST_INIT_VAL; + data &= ~(RP_TXBA1_CM_OVER_PW_BURST_MASK); + data |= RP_TXBA1_CM_OVER_PW_BURST_INIT_VAL; + rp_writel(data, RP_TXBA1, index); + tegra_pcie.num_ports++; pp->index = index; memset(pp->res, 0, sizeof(pp->res)); |