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author | Jin Qian <jqian@nvidia.com> | 2011-08-15 19:32:23 -0700 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:47:21 -0800 |
commit | 7b8232e71a72125f06bc3b1dbfdef36928e24ae6 (patch) | |
tree | f8f2f5f4664e0a8653298e3480916b646a66d0a2 /arch | |
parent | b20d7996604b924cd3fa2aa416b968c6e64d0d46 (diff) |
ARM: tegra: power: setup TTB0 for cacheable memory
Bug 862494
Change-Id: Ib7875ded150b3e9dc288a9ed90f6ded0a37014a3
Reviewed-on: http://git-master/r/47246
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R11be58a9cf3a46fadf985e209e26dc00a8d87c58
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-tegra/pm.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 1c69f6d47910..4456a9cd8ead 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -240,7 +240,8 @@ static __init int create_suspend_pgtable(void) identity_mapping_add(tegra_pgd, IO_IRAM_PHYS, IO_IRAM_PHYS + SECTION_SIZE); - tegra_pgd_phys = virt_to_phys(tegra_pgd); + /* inner/outer write-back/write-allocate, sharable */ + tegra_pgd_phys = (virt_to_phys(tegra_pgd) & PAGE_MASK) | 0x4A; return 0; } |