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authorScott Williams <scwilliams@nvidia.com>2011-07-25 18:31:19 -0700
committerDan Willemsen <dwillemsen@nvidia.com>2011-11-30 21:46:58 -0800
commitdca48c8c55d480bf7c806474bf47b42c3a080d4b (patch)
tree99c503ec0a315d5f513f9f5d13d65160517da778 /arch
parentb9e403190bbbe1225abd87185e7dfb4518a1e992 (diff)
ARM: tegra: power: CPU complex must be suspended on CPU0
All CPUs are not created equal. CPU0 must be the one to perform the CPU complex rail gating action and as such must always be the last CPU taken down. Change-Id: I92d1c1c29305d2bf35a15baa43a6d299806482b7 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Rebase-Id: R5ba8fbba2771a2458fcf27d9d49c964ffbe53c88
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-tegra/cpuidle-t3.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/cpuidle-t3.c b/arch/arm/mach-tegra/cpuidle-t3.c
index 7ea1657dff6b..5614994aa0ab 100644
--- a/arch/arm/mach-tegra/cpuidle-t3.c
+++ b/arch/arm/mach-tegra/cpuidle-t3.c
@@ -305,7 +305,7 @@ void tegra3_idle_lp2(struct cpuidle_device *dev,
cpu_pm_enter();
- if (last_cpu)
+ if (last_cpu && (dev->cpu == 0))
tegra3_idle_enter_lp2_cpu_0(dev, state, request);
else
tegra3_idle_enter_lp2_cpu_n(dev, state, request);