diff options
| author | Alex Frid <afrid@nvidia.com> | 2011-07-07 21:37:45 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:47:28 -0800 |
| commit | ef4041b7783a32f7b49c22f4d3d3eefdb0fee168 (patch) | |
| tree | a0542731e16bae1a9f63a782c2db26ee5c3dbc7b /arch | |
| parent | 610c9c91b5f7cc631bc5e3890580cd2ca137af20 (diff) | |
ARM: tegra: clock: Save/restore Tegra3 audio sync clocks
Save/restore Tegra3 audio sync clocks on entry/exit to/from deep sleep.
Original-Change-Id: I3a6ddd3d7291760e6b36731d1ec7e401b8081690
Reviewed-on: http://git-master/r/40125
Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com>
Tested-by: Chih-Lung Huang <lhuang@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: Rb26a85d1d08725e6b357a50b53ef1f61d3f52ce4
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-tegra/tegra3_clocks.c | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c index 031d61bac167..c4b1b5342189 100644 --- a/arch/arm/mach-tegra/tegra3_clocks.c +++ b/arch/arm/mach-tegra/tegra3_clocks.c @@ -116,8 +116,14 @@ #define PERIPH_CLK_SOURCE_NUM2 \ ((PERIPH_CLK_SOURCE_SE - PERIPH_CLK_SOURCE_G3D2) / 4 + 1) +#define AUDIO_DLY_CLK 0x49c +#define AUDIO_SYNC_CLK_SPDIF 0x4b4 +#define PERIPH_CLK_SOURCE_NUM3 \ + ((AUDIO_SYNC_CLK_SPDIF - AUDIO_DLY_CLK) / 4 + 1) + #define PERIPH_CLK_SOURCE_NUM (PERIPH_CLK_SOURCE_NUM1 + \ - PERIPH_CLK_SOURCE_NUM2) + PERIPH_CLK_SOURCE_NUM2 + \ + PERIPH_CLK_SOURCE_NUM3) #define CPU_SOFTRST_CTRL 0x380 @@ -4216,6 +4222,9 @@ void tegra_clk_suspend(void) off+=4) { *ctx++ = clk_readl(off); } + for (off = AUDIO_DLY_CLK; off <= AUDIO_SYNC_CLK_SPDIF; off+=4) { + *ctx++ = clk_readl(off); + } *ctx++ = clk_readl(RST_DEVICES_L); *ctx++ = clk_readl(RST_DEVICES_H); @@ -4300,6 +4309,9 @@ void tegra_clk_resume(void) off += 4) { clk_writel(*ctx++, off); } + for (off = AUDIO_DLY_CLK; off <= AUDIO_SYNC_CLK_SPDIF; off+=4) { + clk_writel(*ctx++, off); + } wmb(); clk_writel(*ctx++, RST_DEVICES_L); |