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authorKe Wei <kewei@marvell.com>2008-05-23 10:23:22 +0200
committerLennert Buytenhek <buytenh@marvell.com>2008-06-22 22:45:01 +0200
commit1219715de70956557b9dedf3ee021a73d4f4ec52 (patch)
tree8d778c742bb7e5a0f087e8f8f88a210da6f0125a /arch
parentab6d15d50637fc25ee941710b23fed09ceb28db3 (diff)
[ARM] Orion: add a separate BRIDGE_INT_TIMER1_CLR define
Some Feroceon-based SoCs have an MBUS bridge interrupt controller that requires writing a one instead of a zero to clear edge interrupt sources such as timer expiry. This patch adds a new BRIDGE_INT_TIMER1_CLR define, which platform code can set to either ~BRIDGE_INT_TIMER1 (write-zero-to-clear) or BRIDGE_INT_TIMER1 (write-one-to-clear) depending on the platform. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/plat-orion/time.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c
index 28b5285446e8..93c4ef9f0067 100644
--- a/arch/arm/plat-orion/time.c
+++ b/arch/arm/plat-orion/time.c
@@ -74,7 +74,7 @@ orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
/*
* Clear and enable clockevent timer interrupt.
*/
- writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE);
+ writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);
u = readl(BRIDGE_MASK);
u |= BRIDGE_INT_TIMER1;
@@ -138,7 +138,7 @@ orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
/*
* ACK pending timer interrupt.
*/
- writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE);
+ writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);
}
local_irq_restore(flags);
@@ -159,7 +159,7 @@ static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
/*
* ACK timer interrupt and call event handler.
*/
- writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE);
+ writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);
orion_clkevt.event_handler(&orion_clkevt);
return IRQ_HANDLED;