diff options
author | Diwakar Tundlam <dtundlam@nvidia.com> | 2011-08-05 17:12:36 -0700 |
---|---|---|
committer | Niket Sirsi <nsirsi@nvidia.com> | 2011-08-22 17:29:29 -0700 |
commit | 24d6d42fd0e853fb6ca8dc961e42a3eebde1a0d7 (patch) | |
tree | 2015f30100d4f402bd1289f145cbb74c6adac63c /arch | |
parent | a980c98794ec0f13d8fafee90c1b5ad82748e423 (diff) |
ARM: Tegra: cpu: Set G-CPU L2 cache latency to 0x777/777
Bugid 860893
Change-Id: I8c04b6193b19ba847df40cc88bb5c49782817428
Reviewed-on: http://git-master/r/45880
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-tegra/common.c | 4 | ||||
-rw-r--r-- | arch/arm/mach-tegra/cortex-a9.S | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index a4aa23710cc3..5d280c6ffd91 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -180,8 +180,8 @@ void __init tegra_init_cache(void) writel(0x221, p + L2X0_TAG_LATENCY_CTRL); writel(0x221, p + L2X0_DATA_LATENCY_CTRL); } else { - writel(0x441, p + L2X0_TAG_LATENCY_CTRL); - writel(0x551, p + L2X0_DATA_LATENCY_CTRL); + writel(0x777, p + L2X0_TAG_LATENCY_CTRL); + writel(0x777, p + L2X0_DATA_LATENCY_CTRL); } #else writel(0x770, p + L2X0_TAG_LATENCY_CTRL); diff --git a/arch/arm/mach-tegra/cortex-a9.S b/arch/arm/mach-tegra/cortex-a9.S index 96f915725eb1..a2884b839e7b 100644 --- a/arch/arm/mach-tegra/cortex-a9.S +++ b/arch/arm/mach-tegra/cortex-a9.S @@ -661,8 +661,8 @@ ENTRY(__cortex_a9_l2x0_restart) mov32 r5, (TEGRA_FLOW_CTRL_BASE-IO_PPSB_PHYS+IO_PPSB_VIRT) ldr r5, [r5, #0x2C] @ FLOW_CTRL_CLUSTER_CONTROL ands r5, r5, #1 @ 0 == G cluster, 1 == LP cluster - movweq r5, #0x441 @ G tag - movweq r6, #0x551 @ G data + movweq r5, #0x777 @ G tag + movweq r6, #0x777 @ G data movwne r5, #0x221 @ LP tag movwne r6, #0x221 @ LP data #endif |