tegra: OWR the offset calculation was not being done properly

The Offset calculation was done wrong while doing a read operation.
This has been fixed now.
The total size of the EPROM is being retrieved from the odm query, this
value may vary for vendors.

Addresses Bug 509729

4 files changed, 21 insertions, 5 deletions

diff --git a/arch/arm/mach-tegra/include/nverrval.h b/arch/arm/mach-tegra/include/nverrval.h
index 87b2f4e6bc62..8be2cbf92093 100644..100755
--- a/arch/arm/mach-tegra/include/nverrval.h
+++ b/arch/arm/mach-tegra/include/nverrval.h
@@ -149,6 +149,7 @@ NVERROR(IdeWriteError,                      0x00046002, "Ide write error")
 NVERROR(OwrReadFailed,                      0x00047000, "OWR data reading failed")
 NVERROR(OwrWriteFailed,                     0x00047001, "OWR data write failed")
 NVERROR(OwrBitTransferFailed,               0x00047002, "OWR bit transfer failed")
+NVERROR(OwrInvalidOffset,                   0x00047003, "OWR invalid offset")
 
 /* Nv2D error codes */
 NVERROR(InvalidOperation,                   0x00050000, "invalid operation")
diff --git a/arch/arm/mach-tegra/include/nvodm_query.h b/arch/arm/mach-tegra/include/nvodm_query.h
index e15e1859b9d3..3cd5e135b5d9 100644..100755
--- a/arch/arm/mach-tegra/include/nvodm_query.h
+++ b/arch/arm/mach-tegra/include/nvodm_query.h
@@ -391,6 +391,8 @@ typedef struct
 
     /** OWR device memory address size. */
     NvU32 AddressSize;
+    /** OWR device Memory size. */
+    NvU32 MemorySize;
 } NvOdmQueryOwrDeviceInfo;
 
 /**
diff --git a/arch/arm/mach-tegra/nvrm/io/ap20/ap20rm_owr.c b/arch/arm/mach-tegra/nvrm/io/ap20/ap20rm_owr.c
index fe2d64c8953e..2ca97f277cbb 100644..100755
--- a/arch/arm/mach-tegra/nvrm/io/ap20/ap20rm_owr.c
+++ b/arch/arm/mach-tegra/nvrm/io/ap20/ap20rm_owr.c
@@ -101,7 +101,8 @@
 #define OWR_DEFAULT_PRESENCE_CLK_VALUE    0x50
 /* Default OWR device memory offset size */
 #define OWR_DEFAULT_OFFSET_SIZE_BYTES   2
-
+/* Default OWR memory size */
+#define OWR_DEFAULT_MEMORY_SIZE     0x80
 
 /* Register access Macros */
 #define OWR_REGR(OwrVirtualAddress, reg) \
@@ -299,15 +300,26 @@ PrivOwrReadFifo(
     NvU32 ReadDataClk = OWR_DEFAULT_READ_DTA_CLK_VALUE;
     NvU32 PresenceClk = OWR_DEFAULT_PRESENCE_CLK_VALUE;
     NvU32 i = 0;
+    NvU32 size = OWR_DEFAULT_MEMORY_SIZE;
+    NvU32 value = 0;
 
     if (pOdmInfo)
     {
         ReadDataClk = pOdmInfo->ReadDataSampleClk;
         PresenceClk = pOdmInfo->PresenceSampleClk;
-    }    
-    
+        size = pOdmInfo->MemorySize;
+    }
+
+    if ( Transaction.Offset >= size)
+    {
+        status = NvError_OwrInvalidOffset;
+        return status;
+    }
     // Configure the number of bytes to read
-    OWR_REGW(pOwrInfo->pOwrVirtualAddress, EPROM, (NumBytes - 1));
+    value = size - Transaction.Offset - 1;
+    OWR_REGW(pOwrInfo->pOwrVirtualAddress,
+                    EPROM,
+                    value);
 
     // Configure the read, presence sample clock and
     // configure for byte transfer mode
diff --git a/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query.c b/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query.c
index ed5e81da1d38..622a7663e777 100644..100755
--- a/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query.c
+++ b/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query.c
@@ -116,7 +116,8 @@ static const NvOdmQueryOwrDeviceInfo s_NvOdmQueryOwrInfo = {
 
     0x7, /* Read data sample clk */
     0x50, /* Presence sample clk */
-    2  /* Memory address size */
+    2,  /* Memory address size */
+    0x80 /* Memory size*/
 };
 
 static const NvOdmSdramControllerConfigAdv s_NvOdmE1109EmcConfigTable[] =