ENGR00118047 iMX23 Fix DVFS Can't change frequency and voltage

Policy min and max is set to current frequency.
emi.S use wrong register address
Some line miss at clock.c when port from 28 kernel.

Signed-off-by: Frank.Li <Frank.Li@freescale.com>

5 files changed, 97 insertions, 82 deletions

diff --git a/arch/arm/mach-stmp378x/emi.S b/arch/arm/mach-stmp378x/emi.S
index 2b7625597ed3..f4072ff33b24 100644
--- a/arch/arm/mach-stmp378x/emi.S
+++ b/arch/arm/mach-stmp378x/emi.S
@@ -20,9 +20,11 @@
 #include <mach/hardware.h>
 #include <asm/system.h>
 #include <asm/pgtable-hwdef.h>
+#include <mach/platform.h>
 #include <mach/regs-power.h>
 #include <mach/regs-clkctrl.h>
 
+/* TODO should be move to clock.h */
 #define SCALING_DATA_EMI_DIV_OFFSET     0
 #define SCALING_DATA_FRAC_DIV_OFFSET    4
 #define SCALING_DATA_CUR_FREQ_OFFSET    8
@@ -91,16 +93,16 @@ ENTRY(stmp3xxx_ram_freq_scale)
 
 100:
 	@ RAM to clk from xtal
-	mov	r0, #(HW_CLKCTRL_CLKSEQ & 0x000000FF)
-	orr	r0, r0, #(HW_CLKCTRL_CLKSEQ & 0x0000FF00)
-	orr	r0, r0, #(HW_CLKCTRL_CLKSEQ & 0x00FF0000)
-	orr	r0, r0, #(HW_CLKCTRL_CLKSEQ & 0xFF000000)
+	mov	r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x000000FF)
+	orr	r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x0000FF00)
+	orr	r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x00FF0000)
+	orr	r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0xFF000000)
 	mov	r1, #(1<<6)
 	str	r1, [r0, #4]
-	mov	r0, #(HW_CLKCTRL_EMI & 0x000000FF)
-	orr	r0, r0, #(HW_CLKCTRL_EMI & 0x0000FF00)
-	orr	r0, r0, #(HW_CLKCTRL_EMI & 0x00FF0000)
-	orr	r0, r0, #(HW_CLKCTRL_EMI & 0xFF000000)
+	mov	r0, #(HW_CLKCTRL_EMI_ADDR & 0x000000FF)
+	orr	r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x0000FF00)
+	orr	r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x00FF0000)
+	orr	r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0xFF000000)
 101:	ldr     r1, [r0]
 	tst     r1, #BM_CLKCTRL_EMI_BUSY_REF_XTAL
 	bne     101b
@@ -108,17 +110,17 @@ ENTRY(stmp3xxx_ram_freq_scale)
 	bl	__stmp_emi_set_values
 
 	@ EMI back to PLL
-	mov	r0, #(HW_CLKCTRL_CLKSEQ & 0x000000FF)
-	orr	r0, r0, #(HW_CLKCTRL_CLKSEQ & 0x0000FF00)
-	orr	r0, r0, #(HW_CLKCTRL_CLKSEQ & 0x00FF0000)
-	orr	r0, r0, #(HW_CLKCTRL_CLKSEQ & 0xFF000000)
+	mov	r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x000000FF)
+	orr	r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x0000FF00)
+	orr	r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x00FF0000)
+	orr	r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0xFF000000)
 	mov	r1, #(1<<6)
 	str	r1, [r0, #8]
 
-	mov	r0, #(HW_CLKCTRL_EMI & 0x000000FF)
-	orr	r0, r0, #(HW_CLKCTRL_EMI & 0x0000FF00)
-	orr	r0, r0, #(HW_CLKCTRL_EMI & 0x00FF0000)
-	orr	r0, r0, #(HW_CLKCTRL_EMI & 0xFF000000)
+	mov	r0, #(HW_CLKCTRL_EMI_ADDR & 0x000000FF)
+	orr	r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x0000FF00)
+	orr	r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x00FF0000)
+	orr	r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0xFF000000)
 1:	ldr	r1, [r0]
 	tst	r1, #BM_CLKCTRL_EMI_BUSY_REF_EMI
 	bne	1b
@@ -151,3 +153,4 @@ __stmp_flush_cache_addr:
 
 ENTRY(stmp3xxx_ram_funcs_sz)
 	.word	. - stmp3xxx_ram_freq_scale
+
diff --git a/arch/arm/mach-stmp378x/emi.inc b/arch/arm/mach-stmp378x/emi.inc
index 0e003c994a2b..3fc5f89543e9 100644
--- a/arch/arm/mach-stmp378x/emi.inc
+++ b/arch/arm/mach-stmp378x/emi.inc
@@ -17,17 +17,17 @@
  */
 __stmp_emi_set_values:
 	stmfd	r9!, {r0 - r4, lr}
-	mov	r1, #(HW_CLKCTRL_EMI & 0x000000FF)
-	orr	r1, r1, #(HW_CLKCTRL_EMI & 0x0000FF00)
-	orr	r1, r1, #(HW_CLKCTRL_EMI & 0x00FF0000)
-	orr	r1, r1, #(HW_CLKCTRL_EMI & 0xFF000000)
+	mov	r1, #(HW_CLKCTRL_EMI_ADDR & 0x000000FF)
+	orr	r1, r1, #(HW_CLKCTRL_EMI_ADDR & 0x0000FF00)
+	orr	r1, r1, #(HW_CLKCTRL_EMI_ADDR & 0x00FF0000)
+	orr	r1, r1, #(HW_CLKCTRL_EMI_ADDR & 0xFF000000)
 
 	mov	r3, #BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE
 
-	mov	r0, #(HW_CLKCTRL_FRAC & 0x000000FF)
-	orr	r0, r0, #(HW_CLKCTRL_FRAC & 0x0000FF00)
-	orr	r0, r0, #(HW_CLKCTRL_FRAC & 0x00FF0000)
-	orr	r0, r0, #(HW_CLKCTRL_FRAC & 0xFF000000)
+	mov	r0, #(HW_CLKCTRL_FRAC_ADDR & 0x000000FF)
+	orr	r0, r0, #(HW_CLKCTRL_FRAC_ADDR & 0x0000FF00)
+	orr	r0, r0, #(HW_CLKCTRL_FRAC_ADDR & 0x00FF0000)
+	orr	r0, r0, #(HW_CLKCTRL_FRAC_ADDR & 0xFF000000)
 	ldr	r2, [r0]
 
 	and	r4, r2, #BM_CLKCTRL_FRAC_EMIFRAC
@@ -705,3 +705,4 @@ __stmp_dram_saved_values:
 	.word	0
 	.word	40
 	.word	0
+
diff --git a/arch/arm/mach-stmp378x/sleep.S b/arch/arm/mach-stmp378x/sleep.S
index acbfa326bebd..6789a75c4c07 100644
--- a/arch/arm/mach-stmp378x/sleep.S
+++ b/arch/arm/mach-stmp378x/sleep.S
@@ -18,7 +18,9 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 #include <mach/hardware.h>
+#include <asm/system.h>
 #include <asm/pgtable-hwdef.h>
+#include <mach/platform.h>
 #include <mach/regs-power.h>
 #include <mach/regs-clkctrl.h>
 #include "sleep.h"
@@ -76,10 +78,10 @@ ENTRY(stmp37xx_cpu_standby)
 	mov	lr, pc
 	b	stmp3xxx_ram_24M_set_timings
 
-	mov	r0, #(HW_CLKCTRL_CLKSEQ & 0x000000FF)
-	orr	r0, r0, #(HW_CLKCTRL_CLKSEQ & 0x0000FF00)
-	orr	r0, r0, #(HW_CLKCTRL_CLKSEQ & 0x00FF0000)
-	orr	r0, r0, #(HW_CLKCTRL_CLKSEQ & 0xFF000000)
+	mov	r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x000000FF)
+	orr	r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x0000FF00)
+	orr	r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x00FF0000)
+	orr	r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0xFF000000)
 	ldr	r4, [r0]
 	mov	r1, #(1<<6)
 	str	r1, [r0, #4]
@@ -88,33 +90,33 @@ ENTRY(stmp37xx_cpu_standby)
 	bne	1b
 
 	@ save RAM divisors
-	mov	r0, #(HW_CLKCTRL_FRAC & 0x000000FF)
-	orr	r0, r0, #(HW_CLKCTRL_FRAC & 0x0000FF00)
-	orr	r0, r0, #(HW_CLKCTRL_FRAC & 0x00FF0000)
-	orr	r0, r0, #(HW_CLKCTRL_FRAC & 0xFF000000)
+	mov	r0, #(HW_CLKCTRL_FRAC_ADDR & 0x000000FF)
+	orr	r0, r0, #(HW_CLKCTRL_FRAC_ADDR & 0x0000FF00)
+	orr	r0, r0, #(HW_CLKCTRL_FRAC_ADDR & 0x00FF0000)
+	orr	r0, r0, #(HW_CLKCTRL_FRAC_ADDR & 0xFF000000)
 	ldr	r8, [r0]
 	and	r8, r8, #(0x3F << 8)
 	lsr	r8, r8, #8
-	mov	r0, #(HW_CLKCTRL_EMI & 0x000000FF)
-	orr	r0, r0, #(HW_CLKCTRL_EMI & 0x0000FF00)
-	orr	r0, r0, #(HW_CLKCTRL_EMI & 0x00FF0000)
-	orr	r0, r0, #(HW_CLKCTRL_EMI & 0xFF000000)
+	mov	r0, #(HW_CLKCTRL_EMI_ADDR & 0x000000FF)
+	orr	r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x0000FF00)
+	orr	r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x00FF0000)
+	orr	r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0xFF000000)
 	ldr	r7, [r0]
 	and	r7, r7, #0x3F
 
 	@ shut the PLL down
-	mov	r0, #(HW_CLKCTRL_PLLCTRL0 & 0x000000FF)
-	orr	r0, r0, #(HW_CLKCTRL_PLLCTRL0 & 0x0000FF00)
-	orr	r0, r0, #(HW_CLKCTRL_PLLCTRL0 & 0x00FF0000)
-	orr	r0, r0, #(HW_CLKCTRL_PLLCTRL0 & 0xFF000000)
+	mov	r0, #(HW_CLKCTRL_PLLCTRL0_ADDR & 0x000000FF)
+	orr	r0, r0, #(HW_CLKCTRL_PLLCTRL0_ADDR & 0x0000FF00)
+	orr	r0, r0, #(HW_CLKCTRL_PLLCTRL0_ADDR & 0x00FF0000)
+	orr	r0, r0, #(HW_CLKCTRL_PLLCTRL0_ADDR & 0xFF000000)
 	mov	r1, #(1<<16)
 	str	r1, [r0, #0x08]	@ clear
 
 	@ set vddd to minimum
-	mov	r0, #(HW_POWER_VDDDCTRL & 0x000000FF)
-	orr	r0, r0, #(HW_POWER_VDDDCTRL & 0x0000FF00)
-	orr	r0, r0, #(HW_POWER_VDDDCTRL & 0x00FF0000)
-	orr	r0, r0, #(HW_POWER_VDDDCTRL & 0xFF000000)
+	mov	r0, #(HW_POWER_VDDDCTRL_ADDR & 0x000000FF)
+	orr	r0, r0, #(HW_POWER_VDDDCTRL_ADDR & 0x0000FF00)
+	orr	r0, r0, #(HW_POWER_VDDDCTRL_ADDR & 0x00FF0000)
+	orr	r0, r0, #(HW_POWER_VDDDCTRL_ADDR & 0xFF000000)
 	ldr	r6, [r0]
 	bic	r1, r6, #0xFF
 	bic	r1, r1, #0x30
@@ -129,10 +131,10 @@ ENTRY(stmp37xx_cpu_standby)
 #endif
 
 	@ do enter standby
-	mov	r0, #(HW_CLKCTRL_CPU & 0x000000FF)
-	orr	r0, r0, #(HW_CLKCTRL_CPU & 0x0000FF00)
-	orr	r0, r0, #(HW_CLKCTRL_CPU & 0x00FF0000)
-	orr	r0, r0, #(HW_CLKCTRL_CPU & 0xFF000000)
+	mov	r0, #(HW_CLKCTRL_CPU_ADDR & 0x000000FF)
+	orr	r0, r0, #(HW_CLKCTRL_CPU_ADDR & 0x0000FF00)
+	orr	r0, r0, #(HW_CLKCTRL_CPU_ADDR & 0x00FF0000)
+	orr	r0, r0, #(HW_CLKCTRL_CPU_ADDR & 0xFF000000)
 	mov	r1, #(1<<12)
 	str	r1, [r0, #4]
 	mov	r2, #0
@@ -149,10 +151,10 @@ ENTRY(stmp37xx_cpu_standby)
 
 #ifdef CONFIG_STMP378X_RAM_FREQ_SCALING
 	@ restore vddd
-	mov	r0, #(HW_POWER_VDDDCTRL & 0x000000FF)
-	orr	r0, r0, #(HW_POWER_VDDDCTRL & 0x0000FF00)
-	orr	r0, r0, #(HW_POWER_VDDDCTRL & 0x00FF0000)
-	orr	r0, r0, #(HW_POWER_VDDDCTRL & 0xFF000000)
+	mov	r0, #(HW_POWER_VDDDCTRL_ADDR & 0x000000FF)
+	orr	r0, r0, #(HW_POWER_VDDDCTRL_ADDR & 0x0000FF00)
+	orr	r0, r0, #(HW_POWER_VDDDCTRL_ADDR & 0x00FF0000)
+	orr	r0, r0, #(HW_POWER_VDDDCTRL_ADDR & 0xFF000000)
 	ldr	r1, [r0]
 	str	r6, [r0]
 	/* now wait 1000 us = 24000 cycles */
@@ -163,10 +165,10 @@ ENTRY(stmp37xx_cpu_standby)
 	nop
 
 	@ put the PLL back up
-	mov	r0, #(HW_CLKCTRL_PLLCTRL0 & 0x000000FF)
-	orr	r0, r0, #(HW_CLKCTRL_PLLCTRL0 & 0x0000FF00)
-	orr	r0, r0, #(HW_CLKCTRL_PLLCTRL0 & 0x00FF0000)
-	orr	r0, r0, #(HW_CLKCTRL_PLLCTRL0 & 0xFF000000)
+	mov	r0, #(HW_CLKCTRL_PLLCTRL0_ADDR & 0x000000FF)
+	orr	r0, r0, #(HW_CLKCTRL_PLLCTRL0_ADDR & 0x0000FF00)
+	orr	r0, r0, #(HW_CLKCTRL_PLLCTRL0_ADDR & 0x00FF0000)
+	orr	r0, r0, #(HW_CLKCTRL_PLLCTRL0_ADDR & 0xFF000000)
 	mov	r1, #(1<<16)
 	str	r1, [r0, #0x04]	@ set
 	/* now wait 10 us = 240 cycles */
@@ -182,17 +184,17 @@ ENTRY(stmp37xx_cpu_standby)
 	mov	lr, pc
 	b	__stmp_emi_set_values
 
-	mov	r0, #(HW_CLKCTRL_CLKSEQ & 0x000000FF)
-	orr	r0, r0, #(HW_CLKCTRL_CLKSEQ & 0x0000FF00)
-	orr	r0, r0, #(HW_CLKCTRL_CLKSEQ & 0x00FF0000)
-	orr	r0, r0, #(HW_CLKCTRL_CLKSEQ & 0xFF000000)
+	mov	r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x000000FF)
+	orr	r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x0000FF00)
+	orr	r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x00FF0000)
+	orr	r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0xFF000000)
 	mov	r1, #(1<<6)
 	str	r1, [r0, #8]
 
-	mov	r0, #(HW_CLKCTRL_EMI & 0x000000FF)
-	orr	r0, r0, #(HW_CLKCTRL_EMI & 0x0000FF00)
-	orr	r0, r0, #(HW_CLKCTRL_EMI & 0x00FF0000)
-	orr	r0, r0, #(HW_CLKCTRL_EMI & 0xFF000000)
+	mov	r0, #(HW_CLKCTRL_EMI_ADDR & 0x000000FF)
+	orr	r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x0000FF00)
+	orr	r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x00FF0000)
+	orr	r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0xFF000000)
 	ldr	r1, [r0]
 	bic	r1, #BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE
 	str	r1, [r0]
@@ -308,10 +310,10 @@ ENTRY(stmp37xx_cpu_suspend)
 	mov	pc, r1
 
 	@ enable internal xtal
-	mov	r2, #(HW_POWER_MINPWR & 0x000000FF)
-	orr	r2, r2, #(HW_POWER_MINPWR & 0x0000FF00)
-	orr	r2, r2, #(HW_POWER_MINPWR & 0x00FF0000)
-	orr	r2, r2, #(HW_POWER_MINPWR & 0xFF000000)
+	mov	r2, #(HW_POWER_MINPWR_ADDR & 0x000000FF)
+	orr	r2, r2, #(HW_POWER_MINPWR_ADDR & 0x0000FF00)
+	orr	r2, r2, #(HW_POWER_MINPWR_ADDR & 0x00FF0000)
+	orr	r2, r2, #(HW_POWER_MINPWR_ADDR & 0xFF000000)
 	ldr	r1, [r2]
 	orr	r1, r1, #(1<<9)
 	str	r1, [r2]
@@ -363,10 +365,10 @@ ENTRY(stmp37xx_cpu_suspend)
 	nop
 
 	@ do enter sleep
-	mov	r0, #(HW_POWER_RESET & 0x000000FF)
-	orr	r0, r0, #(HW_POWER_RESET & 0x0000FF00)
-	orr	r0, r0, #(HW_POWER_RESET & 0x00FF0000)
-	orr	r0, r0, #(HW_POWER_RESET & 0xFF000000)
+	mov	r0, #(HW_POWER_RESET_ADDR & 0x000000FF)
+	orr	r0, r0, #(HW_POWER_RESET_ADDR & 0x0000FF00)
+	orr	r0, r0, #(HW_POWER_RESET_ADDR & 0x00FF0000)
+	orr	r0, r0, #(HW_POWER_RESET_ADDR & 0xFF000000)
 	mov	r1, #0xFF000000
 	orr	r1, r1, #0x00FF0000
 	str	r1, [r0, #8]
@@ -476,9 +478,9 @@ __resume_after_mmu:
 
 #if 0
 	@ select CPU bypass, will be cleared afterwards
-	ldr	r0, =HW_CLKCTRL_CLKSEQ
-	ldr	r2, =HW_CLKCTRL_HBUS
-	ldr	r4, =HW_CLKCTRL_CPU
+	ldr	r0, =HW_CLKCTRL_CLKSEQ_ADDR
+	ldr	r2, =HW_CLKCTRL_HBUS_ADDR
+	ldr	r4, =HW_CLKCTRL_CPU_ADDR
 	mov	r1, #(1<<7)
 	ldr	r3, [r2]
 	bic	r3, r3, #BM_CLKCTRL_HBUS_DIV
diff --git a/arch/arm/plat-stmp3xxx/clock.c b/arch/arm/plat-stmp3xxx/clock.c
index 68241827821b..dcbabb7eca7e 100644
--- a/arch/arm/plat-stmp3xxx/clock.c
+++ b/arch/arm/plat-stmp3xxx/clock.c
@@ -3,7 +3,7 @@
  *
  * Author: Vitaly Wool <vital@embeddedalley.com>
  *
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
  * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
  */
 
@@ -15,7 +15,6 @@
  * http://www.opensource.org/licenses/gpl-license.html
  * http://www.gnu.org/copyleft/gpl.html
  */
-#define DEBUG
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/init.h>
@@ -359,6 +358,7 @@ static int cpu_set_rate(struct clk *clk, u32 rate)
 		reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
 		reg_val &= ~0x3F;
 		reg_val |= clkctrl_cpu;
+
 		__raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
 
 		for (i = 10000; i; i--)
@@ -531,10 +531,15 @@ static int clkseq_set_parent(struct clk *clk, struct clk *parent)
 
 			hbus_val &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN |
 				      BM_CLKCTRL_HBUS_DIV);
+			hbus_val |= 1;
+
 			clk->saved_div = cpu_val & BM_CLKCTRL_CPU_DIV_CPU;
 			cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU;
 			cpu_val |= 1;
 
+			__raw_writel(1 << clk->bypass_shift,
+					clk->bypass_reg + shift);
+
 			if (machine_is_stmp378x()) {
 				__raw_writel(hbus_val,
 					REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS);
@@ -563,10 +568,12 @@ static int clkseq_set_parent(struct clk *clk, struct clk *parent)
 					REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
 				hclk.rate = 0;
 			}
-		}
-#endif
+		} else
+			__raw_writel(1 << clk->bypass_shift,
+					clk->bypass_reg + shift);
+#else
 		__raw_writel(1 << clk->bypass_shift, clk->bypass_reg + shift);
-
+#endif
 		ret = 0;
 	}
 
diff --git a/arch/arm/plat-stmp3xxx/cpufreq.c b/arch/arm/plat-stmp3xxx/cpufreq.c
index 533d1ecd9c8e..89339aea7cc5 100644
--- a/arch/arm/plat-stmp3xxx/cpufreq.c
+++ b/arch/arm/plat-stmp3xxx/cpufreq.c
@@ -436,8 +436,10 @@ static int __init stmp3xxx_cpu_init(struct cpufreq_policy *policy)
 
 	pr_debug("got CPU clock rate %d\n", policy->cur);
 	policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
-	policy->cpuinfo.min_freq = profiles[0].cpu;
-	policy->cpuinfo.max_freq = profiles[ARRAY_SIZE(profiles) - 1].cpu;
+	policy->min = policy->cpuinfo.min_freq = profiles[0].cpu;
+	policy->max = policy->cpuinfo.max_freq =
+			profiles[ARRAY_SIZE(profiles) - 1].cpu;
+
 	policy->cpuinfo.transition_latency = 1000000; /* 1 ms, assumed */
 	clk_put(cpu_clk);