Merge remote branch 'fsl-linux-sdk/imx_3.0.15' into imx_3.0.15_android

Conflicts:
	arch/arm/mach-mx6/devices-imx6q.h
	drivers/power/sabresd_battery.c

16 files changed, 387 insertions, 197 deletions

diff --git a/arch/arm/configs/imx6_defconfig b/arch/arm/configs/imx6_defconfig
index 48cb76a123d1..cce0e2124ecd 100644
--- a/arch/arm/configs/imx6_defconfig
+++ b/arch/arm/configs/imx6_defconfig
@@ -2561,43 +2561,44 @@ CONFIG_CRYPTO=y
 #
 CONFIG_CRYPTO_ALGAPI=y
 CONFIG_CRYPTO_ALGAPI2=y
-CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_AEAD=y
 CONFIG_CRYPTO_AEAD2=y
 CONFIG_CRYPTO_BLKCIPHER=y
 CONFIG_CRYPTO_BLKCIPHER2=y
 CONFIG_CRYPTO_HASH=y
 CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=y
 CONFIG_CRYPTO_RNG2=y
 CONFIG_CRYPTO_PCOMP2=y
 CONFIG_CRYPTO_MANAGER=y
 CONFIG_CRYPTO_MANAGER2=y
-CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
-# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
+CONFIG_CRYPTO_GF128MUL=y
 # CONFIG_CRYPTO_NULL is not set
 # CONFIG_CRYPTO_PCRYPT is not set
 CONFIG_CRYPTO_WORKQUEUE=y
 # CONFIG_CRYPTO_CRYPTD is not set
-CONFIG_CRYPTO_AUTHENC=m
+CONFIG_CRYPTO_AUTHENC=y
 CONFIG_CRYPTO_TEST=m
 # CONFIG_CRYPTO_CRYPTODEV is not set
 
 #
 # Authenticated Encryption with Associated Data
 #
-# CONFIG_CRYPTO_CCM is not set
-# CONFIG_CRYPTO_GCM is not set
-# CONFIG_CRYPTO_SEQIV is not set
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_SEQIV=y
 
 #
 # Block modes
 #
 CONFIG_CRYPTO_CBC=y
-# CONFIG_CRYPTO_CTR is not set
-# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_CTR=y
+CONFIG_CRYPTO_CTS=y
 CONFIG_CRYPTO_ECB=y
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_PCBC is not set
-# CONFIG_CRYPTO_XTS is not set
+CONFIG_CRYPTO_LRW=y
+CONFIG_CRYPTO_PCBC=y
+CONFIG_CRYPTO_XTS=y
 
 #
 # Hash modes
@@ -2610,7 +2611,7 @@ CONFIG_CRYPTO_ECB=y
 # Digest
 #
 # CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_GHASH is not set
+CONFIG_CRYPTO_GHASH=y
 # CONFIG_CRYPTO_MD4 is not set
 # CONFIG_CRYPTO_MD5 is not set
 CONFIG_CRYPTO_MICHAEL_MIC=y
@@ -2634,7 +2635,7 @@ CONFIG_CRYPTO_ARC4=y
 # CONFIG_CRYPTO_CAMELLIA is not set
 # CONFIG_CRYPTO_CAST5 is not set
 # CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_DES is not set
+CONFIG_CRYPTO_DES=y
 # CONFIG_CRYPTO_FCRYPT is not set
 # CONFIG_CRYPTO_KHAZAD is not set
 # CONFIG_CRYPTO_SALSA20 is not set
@@ -2657,12 +2658,12 @@ CONFIG_CRYPTO_LZO=y
 # CONFIG_CRYPTO_USER_API_HASH is not set
 # CONFIG_CRYPTO_USER_API_SKCIPHER is not set
 CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_DEV_FSL_CAAM=m
+CONFIG_CRYPTO_DEV_FSL_CAAM=y
 CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9
 CONFIG_CRYPTO_DEV_FSL_CAAM_INTC=y
 CONFIG_CRYPTO_DEV_FSL_CAAM_INTC_COUNT_THLD=255
 CONFIG_CRYPTO_DEV_FSL_CAAM_INTC_TIME_THLD=2048
-CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=m
+CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y
 # CONFIG_BINARY_PRINTF is not set
 
 #
diff --git a/arch/arm/configs/imx6s_defconfig b/arch/arm/configs/imx6s_defconfig
index ffb73c81609c..ed5ffbbd0898 100644
--- a/arch/arm/configs/imx6s_defconfig
+++ b/arch/arm/configs/imx6s_defconfig
@@ -260,6 +260,7 @@ CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT=y
 CONFIG_IMX_HAVE_PLATFORM_IMX_SNVS_RTC=y
 CONFIG_IMX_HAVE_PLATFORM_IMX_CAAM=y
 CONFIG_IMX_HAVE_PLATFORM_IMX_I2C=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_KEYPAD=y
 CONFIG_IMX_HAVE_PLATFORM_IMX_SSI=y
 CONFIG_IMX_HAVE_PLATFORM_IMX_ESAI=y
 CONFIG_IMX_HAVE_PLATFORM_IMX_UART=y
@@ -1034,7 +1035,7 @@ CONFIG_KEYBOARD_GPIO=y
 # CONFIG_KEYBOARD_MAX7359 is not set
 # CONFIG_KEYBOARD_MCS is not set
 # CONFIG_KEYBOARD_MPR121 is not set
-# CONFIG_KEYBOARD_IMX is not set
+CONFIG_KEYBOARD_IMX=y
 # CONFIG_KEYBOARD_NEWTON is not set
 # CONFIG_KEYBOARD_OPENCORES is not set
 # CONFIG_KEYBOARD_STOWAWAY is not set
@@ -1055,7 +1056,7 @@ CONFIG_INPUT_TOUCHSCREEN=y
 # CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
 # CONFIG_TOUCHSCREEN_EETI is not set
 CONFIG_TOUCHSCREEN_EGALAX=y
-# CONFIG_TOUCHSCREEN_ELAN is not set
+CONFIG_TOUCHSCREEN_ELAN=y
 # CONFIG_TOUCHSCREEN_FUJITSU is not set
 # CONFIG_TOUCHSCREEN_GUNZE is not set
 # CONFIG_TOUCHSCREEN_ELO is not set
@@ -2626,12 +2627,7 @@ CONFIG_CRYPTO_LZO=y
 # CONFIG_CRYPTO_USER_API_HASH is not set
 # CONFIG_CRYPTO_USER_API_SKCIPHER is not set
 CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_DEV_FSL_CAAM=m
-CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9
-CONFIG_CRYPTO_DEV_FSL_CAAM_INTC=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_INTC_COUNT_THLD=255
-CONFIG_CRYPTO_DEV_FSL_CAAM_INTC_TIME_THLD=2048
-CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=m
+# CONFIG_CRYPTO_DEV_FSL_CAAM is not set
 # CONFIG_BINARY_PRINTF is not set
 
 #
diff --git a/arch/arm/mach-mx6/Kconfig b/arch/arm/mach-mx6/Kconfig
index c6851d064eaa..a96597d2d599 100644
--- a/arch/arm/mach-mx6/Kconfig
+++ b/arch/arm/mach-mx6/Kconfig
@@ -98,6 +98,7 @@ config MACH_MX6SL_ARM2
 	select IMX_HAVE_PLATFORM_IMX_EPDC
 	select IMX_HAVE_PLATFORM_IMX_SPDC
 	select IMX_HAVE_PLATFORM_IMX_PXP
+	select IMX_HAVE_PLATFORM_IMX_KEYPAD
 	help
 	  Include support for i.MX 6Sololite Armadillo2 platform. This includes specific
 	  configurations for the board and its peripherals.
diff --git a/arch/arm/mach-mx6/board-mx6q_arm2.c b/arch/arm/mach-mx6/board-mx6q_arm2.c
index 1b43d5f0d2e4..2f82d0248722 100644
--- a/arch/arm/mach-mx6/board-mx6q_arm2.c
+++ b/arch/arm/mach-mx6/board-mx6q_arm2.c
@@ -322,7 +322,7 @@ static int __init gpmi_nand_platform_init(void)
 }
 
 static struct gpmi_nand_platform_data
-mx6_gpmi_nand_platform_data = {
+mx6_gpmi_nand_platform_data __initdata = {
 	.platform_init           = gpmi_nand_platform_init,
 	.min_prop_delay_in_ns    = 5,
 	.max_prop_delay_in_ns    = 9,
diff --git a/arch/arm/mach-mx6/board-mx6sl_arm2.c b/arch/arm/mach-mx6/board-mx6sl_arm2.c
index 2d42966dbfb1..69fb1ad4c08f 100755
--- a/arch/arm/mach-mx6/board-mx6sl_arm2.c
+++ b/arch/arm/mach-mx6/board-mx6sl_arm2.c
@@ -125,6 +125,9 @@
 #define MX6SL_ARM2_EPDC_PMIC_WAKE	IMX_GPIO_NR(2, 14) /* EPDC_PWRWAKEUP */
 #define MX6SL_ARM2_EPDC_PMIC_INT	IMX_GPIO_NR(2, 12) /* EPDC_PWRINT */
 #define MX6SL_ARM2_EPDC_VCOM		IMX_GPIO_NR(2, 3)
+#define MX6SL_ARM2_ELAN_CE		IMX_GPIO_NR(2, 9)
+#define MX6SL_ARM2_ELAN_INT		IMX_GPIO_NR(2, 10)
+#define MX6SL_ARM2_ELAN_RST		IMX_GPIO_NR(4, 4)
 
 static int max17135_regulator_init(struct max17135 *max17135);
 struct clk *extern_audio_root;
@@ -525,6 +528,9 @@ static struct i2c_board_info mxc_i2c0_board_info[] __initdata = {
 	{
 		I2C_BOARD_INFO("max17135", 0x48),
 		.platform_data = &max17135_pdata,
+	}, {
+		I2C_BOARD_INFO("elan-touch", 0x10),
+		.irq = gpio_to_irq(MX6SL_ARM2_ELAN_INT),
 	},
 };
 
@@ -1042,6 +1048,54 @@ static struct mxc_fb_platform_data fb_data[] = {
 static struct platform_device lcd_wvga_device = {
 	.name = "lcd_seiko",
 };
+
+static int mx6sl_arm2_keymap[] = {
+	KEY(0, 0, KEY_SELECT),
+	KEY(0, 1, KEY_BACK),
+	KEY(0, 2, KEY_F1),
+	KEY(0, 3, KEY_F2),
+
+	KEY(1, 0, KEY_F3),
+	KEY(1, 1, KEY_F4),
+	KEY(1, 2, KEY_F5),
+	KEY(1, 3, KEY_MENU),
+
+	KEY(2, 0, KEY_PREVIOUS),
+	KEY(2, 1, KEY_NEXT),
+	KEY(2, 2, KEY_HOME),
+	KEY(2, 3, KEY_NEXT),
+
+	KEY(3, 0, KEY_UP),
+	KEY(3, 1, KEY_LEFT),
+	KEY(3, 2, KEY_RIGHT),
+	KEY(3, 3, KEY_DOWN),
+};
+
+static const struct matrix_keymap_data mx6sl_arm2_map_data __initconst = {
+	.keymap		= mx6sl_arm2_keymap,
+	.keymap_size	= ARRAY_SIZE(mx6sl_arm2_keymap),
+};
+static void __init elan_ts_init(void)
+{
+	mxc_iomux_v3_setup_multiple_pads(mx6sl_arm2_elan_pads,
+					ARRAY_SIZE(mx6sl_arm2_elan_pads));
+
+	/* ELAN Touchscreen */
+	gpio_request(MX6SL_ARM2_ELAN_INT, "elan-interrupt");
+	gpio_direction_input(MX6SL_ARM2_ELAN_INT);
+
+	gpio_request(MX6SL_ARM2_ELAN_CE, "elan-cs");
+	gpio_direction_output(MX6SL_ARM2_ELAN_CE, 1);
+	gpio_direction_output(MX6SL_ARM2_ELAN_CE, 0);
+
+	gpio_request(MX6SL_ARM2_ELAN_RST, "elan-rst");
+	gpio_direction_output(MX6SL_ARM2_ELAN_RST, 1);
+	gpio_direction_output(MX6SL_ARM2_ELAN_RST, 0);
+	mdelay(1);
+	gpio_direction_output(MX6SL_ARM2_ELAN_RST, 1);
+	gpio_direction_output(MX6SL_ARM2_ELAN_CE, 1);
+}
+
 /*!
  * Board specific initialization.
  */
@@ -1049,6 +1103,8 @@ static void __init mx6_arm2_init(void)
 {
 	mxc_iomux_v3_setup_multiple_pads(mx6sl_arm2_pads, ARRAY_SIZE(mx6sl_arm2_pads));
 
+	elan_ts_init();
+
 	gp_reg_id = "cpu_vddgp";
 	mx6_cpu_regulator_init();
 
@@ -1118,6 +1174,8 @@ static void __init mx6_arm2_init(void)
 	imx6q_add_imx2_wdt(0, NULL);
 
 	imx_add_viv_gpu(&imx6_gpu_data, &imx6q_gpu_pdata);
+	imx6sl_add_imx_keypad(&mx6sl_arm2_map_data);
+	imx6q_add_busfreq();
 }
 
 extern void __iomem *twd_base;
diff --git a/arch/arm/mach-mx6/board-mx6sl_arm2.h b/arch/arm/mach-mx6/board-mx6sl_arm2.h
index 940c46d0e984..b0c262c7e729 100755
--- a/arch/arm/mach-mx6/board-mx6sl_arm2.h
+++ b/arch/arm/mach-mx6/board-mx6sl_arm2.h
@@ -143,6 +143,16 @@ static iomux_v3_cfg_t mx6sl_arm2_pads[] = {
 	MX6SL_PAD_PWM1__PWM1_PWMO,
 	/* LCD power on */
 	MX6SL_PAD_KEY_ROW5__GPIO_4_3,
+
+	/* keypad on E-Ink add-on board */
+	MX6SL_PAD_KEY_COL0__KPP_COL_0,
+	MX6SL_PAD_KEY_COL1__KPP_COL_1,
+	MX6SL_PAD_KEY_COL2__KPP_COL_2,
+	MX6SL_PAD_KEY_COL3__KPP_COL_3,
+	MX6SL_PAD_KEY_ROW0__KPP_ROW_0,
+	MX6SL_PAD_KEY_ROW1__KPP_ROW_1,
+	MX6SL_PAD_KEY_ROW2__KPP_ROW_2,
+	MX6SL_PAD_KEY_ROW3__KPP_ROW_3,
 };
 
 static iomux_v3_cfg_t mx6sl_arm2_epdc_enable_pads[] = {
@@ -302,4 +312,10 @@ static iomux_v3_cfg_t mx6sl_arm2_spdc_disable_pads[] = {
 	MX6SL_PAD_EPDC_PWRWAKEUP__GPIO_2_14,
 };
 
+static iomux_v3_cfg_t mx6sl_arm2_elan_pads[] = {
+	MX6SL_PAD_EPDC_PWRCTRL3__GPIO_2_10,	/* INT */
+	MX6SL_PAD_EPDC_PWRCTRL2__GPIO_2_9,	/* CE */
+	MX6SL_PAD_KEY_COL6__GPIO_4_4,		/* RST */
+};
+
 #endif
diff --git a/arch/arm/mach-mx6/bus_freq.c b/arch/arm/mach-mx6/bus_freq.c
index b573f09c8920..37aec11d0133 100644
--- a/arch/arm/mach-mx6/bus_freq.c
+++ b/arch/arm/mach-mx6/bus_freq.c
@@ -45,14 +45,11 @@
 #include <asm/tlb.h>
 #include "crm_regs.h"
 
-
-#define LPAPM_CLK	24000000
-#define DDR_MED_CLK	400000000
-#define DDR3_NORMAL_CLK	528000000
-#define GPC_PGC_GPU_PGCR_OFFSET		0x260
-#define GPC_CNTR_OFFSET				0x0
-
-
+#define LPAPM_CLK		24000000
+#define DDR_MED_CLK		400000000
+#define DDR3_NORMAL_CLK		528000000
+#define GPC_PGC_GPU_PGCR_OFFSET	0x260
+#define GPC_CNTR_OFFSET		0x0
 
 DEFINE_SPINLOCK(ddr_freq_lock);
 
@@ -91,25 +88,20 @@ struct timeval end_time;
 static int cpu_op_nr;
 static struct cpu_op *cpu_op_tbl;
 static struct clk *pll2_400;
-static struct clk *pll2_200;
+static struct clk *axi_clk;
+static struct clk *ahb_clk;
+static struct clk *periph_clk;
+static struct clk *osc_clk;
 static struct clk *cpu_clk;
 static unsigned int org_ldo;
 static struct clk *pll3;
 static struct clk *pll2;
-static struct clk *periph_clk;
-static struct clk *osc;
+static struct clk *pll3_sw_clk;
+static struct clk *pll2_200;
+static struct clk *mmdc_ch0_axi;
 
 static struct delayed_work low_bus_freq_handler;
-extern void update_usecount(struct clk *clk, bool flag);
 
-static inline void update_periph_clk_parent(struct clk *new_parent)
-{
-	update_usecount(periph_clk->parent, false);
-
-	periph_clk->parent = new_parent;
-
-	update_usecount(periph_clk->parent, true);
-}
 static void reduce_bus_freq_handler(struct work_struct *work)
 {
 	unsigned long reg;
@@ -135,68 +127,88 @@ static void reduce_bus_freq_handler(struct work_struct *work)
 		return;
 	}
 
-	clk_enable(pll3);
-
-	if (lp_audio_freq) {
-		/* Need to ensure that PLL2_PFD_400M is kept ON. */
-		clk_enable(pll2_400);
-		update_ddr_freq(50000000);
-		/* Make sure periph clk's parent also got updated */
-		update_periph_clk_parent(pll2_200);
+	if (!cpu_is_mx6sl()) {
+		clk_enable(pll3);
+
+		if (lp_audio_freq) {
+			/* Need to ensure that PLL2_PFD_400M is kept ON. */
+			clk_enable(pll2_400);
+			update_ddr_freq(50000000);
+			/* Make sure periph clk's parent also got updated */
+			clk_set_parent(periph_clk, pll2_200);
+			audio_bus_freq_mode = 1;
+			low_bus_freq_mode = 0;
+		} else {
+			update_ddr_freq(24000000);
+			/* Make sure periph clk's parent also got updated */
+			clk_set_parent(periph_clk, osc_clk);
+			if (audio_bus_freq_mode)
+				clk_disable(pll2_400);
+			low_bus_freq_mode = 1;
+			audio_bus_freq_mode = 0;
+		}
 
-		audio_bus_freq_mode = 1;
-		low_bus_freq_mode = 0;
-	} else {
-		update_ddr_freq(24000000);
-		/* Make sure periph clk's parent also got updated */
-		update_periph_clk_parent(osc);
-		if (audio_bus_freq_mode)
+		if (med_bus_freq_mode)
 			clk_disable(pll2_400);
+		clk_disable(pll3);
+	} else {
+		/* Set periph_clk to be sourced from OSC_CLK */
+		/* Set MMDC clk to 25MHz. */
+		/* First need to set the divider before changing the parent */
+		/* if parent clock is larger than previous one */
+		clk_set_rate(mmdc_ch0_axi, clk_get_rate(mmdc_ch0_axi) / 2);
+		clk_set_parent(mmdc_ch0_axi, pll3_sw_clk);
+		clk_set_parent(mmdc_ch0_axi, pll2_200);
+		clk_set_rate(mmdc_ch0_axi,
+			     clk_round_rate(mmdc_ch0_axi, LPAPM_CLK));
+
+		/* Set AXI to 24MHz. */
+		clk_set_parent(periph_clk, osc_clk);
+		clk_set_rate(axi_clk, clk_round_rate(axi_clk, LPAPM_CLK));
+		/* Set AHB to 24MHz. */
+		clk_set_rate(ahb_clk, clk_round_rate(ahb_clk, LPAPM_CLK));
+
 		low_bus_freq_mode = 1;
 		audio_bus_freq_mode = 0;
 	}
 
-	if (med_bus_freq_mode)
-		clk_disable(pll2_400);
-
 	high_bus_freq_mode = 0;
 	med_bus_freq_mode = 0;
 
-	if (cpu_is_mx6q()) {
-		/* Disable the brown out detection since we are going to be
-		  * disabling the LDO.
-		  */
-		reg = __raw_readl(ANA_MISC2_BASE_ADDR);
-		reg &= ~ANADIG_ANA_MISC2_REG1_BO_EN;
-		__raw_writel(reg, ANA_MISC2_BASE_ADDR);
-
-		/* Power gate the PU LDO. */
-		/* Power gate the PU domain first. */
-		/* enable power down request */
-		reg = __raw_readl(gpc_base + GPC_PGC_GPU_PGCR_OFFSET);
-		__raw_writel(reg | 0x1, gpc_base + GPC_PGC_GPU_PGCR_OFFSET);
-		/* power down request */
-		reg = __raw_readl(gpc_base + GPC_CNTR_OFFSET);
-		__raw_writel(reg | 0x1, gpc_base + GPC_CNTR_OFFSET);
-		/* Wait for power down to complete. */
-		while (__raw_readl(gpc_base + GPC_CNTR_OFFSET) & 0x1)
-			;
-
-		/* Mask the ANATOP brown out interrupt in the GPC. */
-		reg = __raw_readl(gpc_base + 0x14);
-		reg |= 0x80000000;
-		__raw_writel(reg, gpc_base + 0x14);
-
-		org_ldo = reg = __raw_readl(ANADIG_REG_CORE);
-		reg &= ~(ANADIG_REG_TARGET_MASK << ANADIG_REG1_PU_TARGET_OFFSET);
-		__raw_writel(reg, ANADIG_REG_CORE);
+	/* Disable the brown out detection since we are going to be
+	  * disabling the LDO.
+	  */
+	reg = __raw_readl(ANA_MISC2_BASE_ADDR);
+	reg &= ~ANADIG_ANA_MISC2_REG1_BO_EN;
+	__raw_writel(reg, ANA_MISC2_BASE_ADDR);
+
+	/* Power gate the PU LDO. */
+	/* Power gate the PU domain first. */
+	/* enable power down request */
+	reg = __raw_readl(gpc_base + GPC_PGC_GPU_PGCR_OFFSET);
+	__raw_writel(reg | 0x1, gpc_base + GPC_PGC_GPU_PGCR_OFFSET);
+	/* power down request */
+	reg = __raw_readl(gpc_base + GPC_CNTR_OFFSET);
+	__raw_writel(reg | 0x1, gpc_base + GPC_CNTR_OFFSET);
+	/* Wait for power down to complete. */
+	while (__raw_readl(gpc_base + GPC_CNTR_OFFSET) & 0x1)
+		;
+
+	/* Mask the ANATOP brown out interrupt in the GPC. */
+	reg = __raw_readl(gpc_base + 0x14);
+	reg |= 0x80000000;
+	__raw_writel(reg, gpc_base + 0x14);
+
+	/* PU power gating. */
+	org_ldo = reg = __raw_readl(ANADIG_REG_CORE);
+	reg &= ~(ANADIG_REG_TARGET_MASK << ANADIG_REG1_PU_TARGET_OFFSET);
+	__raw_writel(reg, ANADIG_REG_CORE);
+
+	/* Clear the BO interrupt in the ANATOP. */
+	reg = __raw_readl(ANADIG_MISC1_REG);
+	reg |= 0x80000000;
+	__raw_writel(reg, ANADIG_MISC1_REG);
 
-		/* Clear the BO interrupt in the ANATOP. */
-		reg = __raw_readl(ANADIG_MISC1_REG);
-		reg |= 0x80000000;
-		__raw_writel(reg, ANADIG_MISC1_REG);
-	}
-	clk_disable(pll3);
 	mutex_unlock(&bus_freq_mutex);
 }
 
@@ -212,8 +224,8 @@ int set_low_bus_freq(void)
 	if (!bus_freq_scaling_initialized || !bus_freq_scaling_is_active)
 		return 0;
 
-	/* Don't lower the frequency immediately. Instead scheduled a delayed work
-	  * and drop the freq if the conditions still remain the same.
+	/* Don't lower the frequency immediately. Instead scheduled a delayed
+	  * work and drop the freq if the conditions still remain the same.
 	  */
 	schedule_delayed_work(&low_bus_freq_handler, usecs_to_jiffies(3000000));
 	return 0;
@@ -242,17 +254,25 @@ int set_high_bus_freq(int high_bus_freq)
 		msleep(1);
 
 	if ((high_bus_freq_mode && (high_bus_freq || lp_high_freq)) ||
-		(med_bus_freq_mode && !high_bus_freq && lp_med_freq && !lp_high_freq)) {
+	    (med_bus_freq_mode && !high_bus_freq && lp_med_freq &&
+	     !lp_high_freq)) {
 		mutex_unlock(&bus_freq_mutex);
 		return 0;
 	}
-	clk_enable(pll3);
-
 
 	/* Enable the PU LDO */
-	if (cpu_is_mx6q() && low_bus_freq_mode) {
+	if (low_bus_freq_mode) {
+		/* Set the voltage of VDDSOC as in normal mode. */
 		__raw_writel(org_ldo, ANADIG_REG_CORE);
 
+		/* Need to wait for the regulator to come back up */
+		/*
+		 * Delay time is based on the number of 24MHz clock cycles
+		 * programmed in the ANA_MISC2_BASE_ADDR for each
+		 * 25mV step.
+		 */
+		udelay(150);
+
 		/* enable power up request */
 		reg = __raw_readl(gpc_base + GPC_PGC_GPU_PGCR_OFFSET);
 		__raw_writel(reg | 0x1, gpc_base + GPC_PGC_GPU_PGCR_OFFSET);
@@ -272,32 +292,58 @@ int set_high_bus_freq(int high_bus_freq)
 		reg = __raw_readl(gpc_base + 0x14);
 		reg &= ~0x80000000;
 		__raw_writel(reg, gpc_base + 0x14);
+
+		if (cpu_is_mx6sl()) {
+			/* Set periph_clk to be sourced from pll2_pfd2_400M */
+			/* First need to set the divider before changing the */
+			/* parent if parent clock is larger than previous one */
+			clk_set_rate(ahb_clk, clk_round_rate(ahb_clk,
+							     LPAPM_CLK / 3));
+			clk_set_rate(axi_clk,
+				     clk_round_rate(axi_clk, LPAPM_CLK / 2));
+			clk_set_parent(periph_clk, pll2_400);
+
+			/* Set mmdc_clk_root to be sourced */
+			/* from pll2_pfd2_400M */
+			clk_set_rate(mmdc_ch0_axi,
+				     clk_round_rate(mmdc_ch0_axi,
+						    LPAPM_CLK / 2));
+			clk_set_parent(mmdc_ch0_axi, pll3_sw_clk);
+			clk_set_parent(mmdc_ch0_axi, pll2_400);
+			clk_set_rate(mmdc_ch0_axi,
+				     clk_round_rate(mmdc_ch0_axi, DDR_MED_CLK));
+
+			high_bus_freq_mode = 1;
+			med_bus_freq_mode = 0;
+		}
 	}
 
-	if (high_bus_freq) {
-		update_ddr_freq(ddr_normal_rate);
-		/* Make sure periph clk's parent also got updated */
-		update_periph_clk_parent(pll2);
-		if (med_bus_freq_mode)
+	if (!cpu_is_mx6sl()) {
+		clk_enable(pll3);
+		if (high_bus_freq) {
+			update_ddr_freq(ddr_normal_rate);
+			/* Make sure periph clk's parent also got updated */
+			clk_set_parent(periph_clk, pll2);
+			if (med_bus_freq_mode)
+				clk_disable(pll2_400);
+			high_bus_freq_mode = 1;
+			med_bus_freq_mode = 0;
+		} else {
+			clk_enable(pll2_400);
+			update_ddr_freq(ddr_med_rate);
+			/* Make sure periph clk's parent also got updated */
+			clk_set_parent(periph_clk, pll2_400);
+			high_bus_freq_mode = 0;
+			med_bus_freq_mode = 1;
+		}
+		if (audio_bus_freq_mode)
 			clk_disable(pll2_400);
-		high_bus_freq_mode = 1;
-		med_bus_freq_mode = 0;
-	} else {
-		clk_enable(pll2_400);
-		update_ddr_freq(ddr_med_rate);
-		/* Make sure periph clk's parent also got updated */
-		update_periph_clk_parent(pll2_400);
-		high_bus_freq_mode = 0;
-		med_bus_freq_mode = 1;
+
+		clk_disable(pll3);
 	}
-	if (audio_bus_freq_mode)
-		clk_disable(pll2_400);
-	low_bus_freq_mode = 0;
-	audio_bus_freq_mode = 0;
 
 	low_bus_freq_mode = 0;
-
-	clk_disable(pll3);
+	audio_bus_freq_mode = 0;
 	mutex_unlock(&bus_freq_mutex);
 
 	return 0;
@@ -396,14 +442,14 @@ static int __devinit busfreq_probe(struct platform_device *pdev)
 	}
 
 	pll2_200 = clk_get(NULL, "pll2_200M");
-	if (IS_ERR(pll2_400)) {
+	if (IS_ERR(pll2_200)) {
 		printk(KERN_DEBUG "%s: failed to get pll2_200M\n",
 		       __func__);
 		return PTR_ERR(pll2_200);
 	}
 
 	pll2 = clk_get(NULL, "pll2");
-	if (IS_ERR(pll2_400)) {
+	if (IS_ERR(pll2)) {
 		printk(KERN_DEBUG "%s: failed to get pll2\n",
 		       __func__);
 		return PTR_ERR(pll2);
@@ -423,18 +469,46 @@ static int __devinit busfreq_probe(struct platform_device *pdev)
 		return PTR_ERR(pll3);
 	}
 
+	pll3_sw_clk = clk_get(NULL, "pll3_sw_clk");
+	if (IS_ERR(pll3_sw_clk)) {
+		printk(KERN_DEBUG "%s: failed to get pll3_sw_clk\n",
+		       __func__);
+		return PTR_ERR(pll3_sw_clk);
+	}
+
+	axi_clk = clk_get(NULL, "axi_clk");
+	if (IS_ERR(axi_clk)) {
+		printk(KERN_DEBUG "%s: failed to get axi_clk\n",
+		       __func__);
+		return PTR_ERR(axi_clk);
+	}
+
+	ahb_clk = clk_get(NULL, "ahb");
+	if (IS_ERR(ahb_clk)) {
+		printk(KERN_DEBUG "%s: failed to get ahb_clk\n",
+		       __func__);
+		return PTR_ERR(ahb_clk);
+	}
+
 	periph_clk = clk_get(NULL, "periph_clk");
 	if (IS_ERR(periph_clk)) {
-		printk(KERN_DEBUG "%s: failed to get periph\n",
+		printk(KERN_DEBUG "%s: failed to get periph_clk\n",
 		       __func__);
 		return PTR_ERR(periph_clk);
 	}
 
-	osc = clk_get(NULL, "osc");
-	if (IS_ERR(osc)) {
-		printk(KERN_DEBUG "%s: failed to get osc\n",
+	osc_clk = clk_get(NULL, "osc");
+	if (IS_ERR(osc_clk)) {
+		printk(KERN_DEBUG "%s: failed to get osc_clk\n",
+		       __func__);
+		return PTR_ERR(osc_clk);
+	}
+
+	mmdc_ch0_axi = clk_get(NULL, "mmdc_ch0_axi");
+	if (IS_ERR(mmdc_ch0_axi)) {
+		printk(KERN_DEBUG "%s: failed to get mmdc_ch0_axi\n",
 		       __func__);
-		return PTR_ERR(osc);
+		return PTR_ERR(mmdc_ch0_axi);
 	}
 
 	err = sysfs_create_file(&busfreq_dev->kobj, &dev_attr_enable.attr);
@@ -456,7 +530,7 @@ static int __devinit busfreq_probe(struct platform_device *pdev)
 		ddr_med_rate = DDR_MED_CLK;
 		ddr_normal_rate = DDR3_NORMAL_CLK;
 	}
-	if (cpu_is_mx6dl()) {
+	if (cpu_is_mx6dl() || cpu_is_mx6sl()) {
 		ddr_low_rate = LPAPM_CLK;
 		ddr_normal_rate = ddr_med_rate = DDR_MED_CLK;
 	}
@@ -465,7 +539,8 @@ static int __devinit busfreq_probe(struct platform_device *pdev)
 
 	mutex_init(&bus_freq_mutex);
 
-	init_mmdc_settings();
+	if (!cpu_is_mx6sl())
+		init_mmdc_settings();
 
 	return 0;
 }
diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c
index 975f22cc2263..81456655032e 100644
--- a/arch/arm/mach-mx6/clock.c
+++ b/arch/arm/mach-mx6/clock.c
@@ -5275,6 +5275,9 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc,
 		clk_debug_register(lookups[i].clk);
 	}
 
+	/* Lower the ipg_perclk frequency to 6MHz. */
+	clk_set_rate(&ipg_perclk, 6000000);
+
 	/* Timer needs to be initialized first as the
 	  * the WAIT routines use GPT counter as
 	  * a delay.
@@ -5421,9 +5424,6 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc,
 
 	__raw_writel(0, MXC_CCM_CCGR6);
 
-	/* Lower the ipg_perclk frequency to 6MHz. */
-	clk_set_rate(&ipg_perclk, 6000000);
-
 	/* S/PDIF */
 	clk_set_parent(&spdif0_clk[0], &pll3_pfd_454M);
 
diff --git a/arch/arm/mach-mx6/clock_mx6sl.c b/arch/arm/mach-mx6/clock_mx6sl.c
index 0c17ed4bfd8f..be00867f729c 100755
--- a/arch/arm/mach-mx6/clock_mx6sl.c
+++ b/arch/arm/mach-mx6/clock_mx6sl.c
@@ -183,11 +183,6 @@ static int _clk_enable(struct clk *clk)
 	reg |= MXC_CCM_CCGRx_CG_MASK << clk->enable_shift;
 	__raw_writel(reg, clk->enable_reg);
 
-	if (clk->flags & AHB_HIGH_SET_POINT)
-		lp_high_freq++;
-	else if (clk->flags & AHB_MED_SET_POINT)
-		lp_med_freq++;
-
 	return 0;
 }
 
@@ -197,11 +192,6 @@ static void _clk_disable(struct clk *clk)
 	reg = __raw_readl(clk->enable_reg);
 	reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
 	__raw_writel(reg, clk->enable_reg);
-
-	if (clk->flags & AHB_HIGH_SET_POINT)
-		lp_high_freq--;
-	else if (clk->flags & AHB_MED_SET_POINT)
-		lp_med_freq--;
 }
 
 static void _clk_disable_inwait(struct clk *clk)
@@ -464,6 +454,10 @@ static void _clk_pll_disable(struct clk *clk)
 	unsigned int reg;
 	void __iomem *pllbase;
 
+	if ((arm_needs_pll2_400) && (clk == &pll2_528_bus_main_clk))
+		return;
+
+
 	pllbase = _get_pll_base(clk);
 
 	reg = __raw_readl(pllbase);
@@ -1296,7 +1290,7 @@ static int _clk_periph_set_parent(struct clk *clk, struct clk *parent)
 			;
 
 		reg = __raw_readl(MXC_CCM_CBCDR);
-		/* Set periph_clk_sel to select periph_clk2. */
+		/* Set periph_clk_sel to select periph_clk. */
 		reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL;
 		__raw_writel(reg, MXC_CCM_CBCDR);
 	}
@@ -1554,6 +1548,47 @@ static struct clk mx6per2_clk = {
 	.disable = _clk_disable_inwait,
 };
 
+static int _clk_mmdc_ch1_axi_set_parent(struct clk *clk,
+					       struct clk *parent)
+{
+	u32 reg;
+	int mux;
+
+	mux = _get_mux6(parent, &pll2_528_bus_main_clk, &pll2_pfd2_400M,
+		&pll2_pfd0_352M, &pll2_200M, &pll3_sw_clk, NULL);
+
+	if (mux <= 3) {
+		/* Set the pre_periph2_clk_sel multiplexer */
+		reg = __raw_readl(MXC_CCM_CBCMR);
+		reg &= ~MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK;
+		reg |= mux << MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET;
+		__raw_writel(reg, MXC_CCM_CBCMR);
+
+		/* Set the periph2_clk_sel multiplexer. */
+		reg = __raw_readl(MXC_CCM_CBCDR);
+		reg &= ~MXC_CCM_CBCDR_PERIPH2_CLK_SEL;
+		__raw_writel(reg, MXC_CCM_CBCDR);
+	} else {
+		/* Select PLL3_SW_CLK from the periph2_clk2
+		   multiplexer */
+		reg = __raw_readl(MXC_CCM_CBCMR);
+		reg &= ~MXC_CCM_CBCMR_PERIPH2_CLK2_SEL;
+		__raw_writel(reg, MXC_CCM_CBCMR);
+
+		/* Set the periph2_clk_sel multiplexer. */
+		reg = __raw_readl(MXC_CCM_CBCDR);
+		reg &= ~MXC_CCM_CBCDR_PERIPH2_CLK_SEL;
+		reg |= MXC_CCM_CBCDR_PERIPH2_CLK_SEL;
+		__raw_writel(reg, MXC_CCM_CBCDR);
+	}
+
+	if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
+	     & MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY), SPIN_DELAY))
+		panic("_clk_mmdc_ch1_axi_set_parent failed\n");
+
+	return 0;
+}
+
 static unsigned long _clk_mmdc_ch1_axi_get_rate(struct clk *clk)
 {
 	u32 reg, div;
@@ -1618,6 +1653,7 @@ static struct clk mmdc_ch1_axi_clk[] = {
 	.enable_reg = MXC_CCM_CCGR3,
 	.enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
 	.secondary = &mmdc_ch1_axi_clk[1],
+	.set_parent = _clk_mmdc_ch1_axi_set_parent,
 	.get_rate = _clk_mmdc_ch1_axi_get_rate,
 	.set_rate = _clk_mmdc_ch1_axi_set_rate,
 	.round_rate = _clk_mmdc_ch1_axi_round_rate,
@@ -1941,13 +1977,12 @@ static struct clk ipu2_clk = {
 	.round_rate = _clk_ipu_round_rate,
 	.set_rate = _clk_ipu2_set_rate,
 	.get_rate = _clk_ipu2_get_rate,
-	.flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
 };
 
 static struct clk usdhc_dep_clk = {
 	.parent = &mmdc_ch1_axi_clk[0],
 	.secondary = &mx6per1_clk,
-	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
 	};
 
 static unsigned long _clk_usdhc_round_rate(struct clk *clk,
@@ -2025,7 +2060,6 @@ static struct clk usdhc1_clk = {
 	.round_rate = _clk_usdhc_round_rate,
 	.set_rate = _clk_usdhc1_set_rate,
 	.get_rate = _clk_usdhc1_get_rate,
-	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
 };
 
 static int _clk_usdhc2_set_parent(struct clk *clk, struct clk *parent)
@@ -2083,7 +2117,6 @@ static struct clk usdhc2_clk = {
 	.round_rate = _clk_usdhc_round_rate,
 	.set_rate = _clk_usdhc2_set_rate,
 	.get_rate = _clk_usdhc2_get_rate,
-	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
 };
 
 static int _clk_usdhc3_set_parent(struct clk *clk, struct clk *parent)
@@ -2142,7 +2175,6 @@ static struct clk usdhc3_clk = {
 	.round_rate = _clk_usdhc_round_rate,
 	.set_rate = _clk_usdhc3_set_rate,
 	.get_rate = _clk_usdhc3_get_rate,
-	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
 };
 
 static int _clk_usdhc4_set_parent(struct clk *clk, struct clk *parent)
@@ -2201,7 +2233,6 @@ static struct clk usdhc4_clk = {
 	.round_rate = _clk_usdhc_round_rate,
 	.set_rate = _clk_usdhc4_set_rate,
 	.get_rate = _clk_usdhc4_get_rate,
-	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
 };
 
 static unsigned long _clk_ssi_round_rate(struct clk *clk,
@@ -2373,6 +2404,7 @@ static struct clk ssi1_clk = {
 #else
 	 .secondary = &mmdc_ch1_axi_clk[0],
 #endif
+	.flags  = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
 };
 
 static unsigned long _clk_ssi2_get_rate(struct clk *clk)
@@ -2446,6 +2478,7 @@ static struct clk ssi2_clk = {
 #else
 	 .secondary = &mmdc_ch1_axi_clk[0],
 #endif
+	.flags  = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
 };
 
 static unsigned long _clk_ssi3_get_rate(struct clk *clk)
@@ -2518,6 +2551,7 @@ static struct clk ssi3_clk = {
 #else
 	 .secondary = &mmdc_ch1_axi_clk[0],
 #endif
+	.flags  = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
 };
 
 static unsigned long _clk_epdc_lcdif_pix_round_rate(struct clk *clk,
@@ -3790,7 +3824,6 @@ static struct clk dummy_clk = {
 		.clk = &c, \
 	}
 
-
 static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK(NULL, "osc", osc_clk),
 	_REGISTER_CLOCK(NULL, "ckih", ckih_clk),
@@ -3799,7 +3832,7 @@ static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK(NULL, "pll1_main_clk", pll1_sys_main_clk),
 	_REGISTER_CLOCK(NULL, "pll1_sw_clk", pll1_sw_clk),
 	_REGISTER_CLOCK(NULL, "pll2", pll2_528_bus_main_clk),
-	_REGISTER_CLOCK(NULL, "pll2_pfd2_400M", pll2_pfd2_400M),
+	_REGISTER_CLOCK(NULL, "pll2_pfd_400M", pll2_pfd2_400M),
 	_REGISTER_CLOCK(NULL, "pll2_pfd0_352M", pll2_pfd0_352M),
 	_REGISTER_CLOCK(NULL, "pll2_pfd1_594M", pll2_pfd1_594M),
 	_REGISTER_CLOCK(NULL, "pll2_200M", pll2_200M),
@@ -3807,7 +3840,7 @@ static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK(NULL, "pll3_pfd2_508M", pll3_pfd2_508M),
 	_REGISTER_CLOCK(NULL, "pll3_pfd3_454M", pll3_pfd3_454M),
 	_REGISTER_CLOCK(NULL, "pll3_pfd0_720M", pll3_pfd0_720M),
-	_REGISTER_CLOCK(NULL, "pll3_pfd1_540M", pll3_pfd1_540M),
+	_REGISTER_CLOCK(NULL, "pll3_pfd_540M", pll3_pfd1_540M),
 	_REGISTER_CLOCK(NULL, "pll3_sw_clk", pll3_sw_clk),
 	_REGISTER_CLOCK(NULL, "pll3_120M", pll3_120M),
 	_REGISTER_CLOCK(NULL, "pll3_80M", pll3_80M),
@@ -3866,6 +3899,7 @@ static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK(NULL, "usb_phy4_clk", usb_phy4_clk),
 	_REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk),
 	_REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk),
+	_REGISTER_CLOCK(NULL, "kpp", dummy_clk),
 	_REGISTER_CLOCK(NULL, NULL, aips_tz2_clk),
 	_REGISTER_CLOCK(NULL, NULL, aips_tz1_clk),
 	_REGISTER_CLOCK(NULL, "clko_clk", clko_clk),
@@ -3896,7 +3930,6 @@ static void clk_tree_init(void)
 	if ((reg & MMDC_MDMISC_DDR_TYPE_MASK) ==
 		(0x1 << MMDC_MDMISC_DDR_TYPE_OFFSET)) {
 		clk_set_parent(&periph_clk, &pll2_pfd2_400M);
-		printk(KERN_INFO "Set periph_clk's parent to pll2_pfd2_400M!\n");
 	}
 }
 
@@ -3928,11 +3961,12 @@ int __init mx6sl_clocks_init(unsigned long ckil, unsigned long osc,
 
 	mxc_timer_init(&gpt_clk[0], timer_base, MXC_INT_GPT);
 
-	clk_tree_init();
-
 	/* keep correct count. */
 	clk_enable(&cpu_clk);
 	clk_enable(&periph_clk);
+	clk_enable(&mmdc_ch1_axi_clk);
+
+	clk_tree_init();
 
 	/* Set AHB to 132MHz. */
 	clk_set_rate(&ahb_clk, clk_round_rate(&ahb_clk, 132000000));
@@ -3991,6 +4025,9 @@ int __init mx6sl_clocks_init(unsigned long ckil, unsigned long osc,
 
 	__raw_writel(0, MXC_CCM_CCGR6);
 
+	/* Bypass MMDC_CH0 handshake */
+	__raw_writel(0x20000, MXC_CCM_CCDR);
+
 	/* S/PDIF */
 	clk_set_parent(&spdif0_clk[0], &pll3_pfd3_454M);
 
diff --git a/arch/arm/mach-mx6/cpu.c b/arch/arm/mach-mx6/cpu.c
index 2822d2d7f17c..651b1ffd4344 100644
--- a/arch/arm/mach-mx6/cpu.c
+++ b/arch/arm/mach-mx6/cpu.c
@@ -152,6 +152,20 @@ static int __init post_cpu_init(void)
 	gpc_base = MX6_IO_ADDRESS(GPC_BASE_ADDR);
 	ccm_base = MX6_IO_ADDRESS(CCM_BASE_ADDR);
 
+	/* enable AXI cache for VDOA/VPU/IPU
+	 * set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
+	 * clear OCRAM_CTL bits to disable pipeline control
+	 */
+	reg = __raw_readl(IOMUXC_GPR3);
+	reg &= ~IOMUXC_GPR3_OCRAM_CTL_EN;
+	__raw_writel(reg, IOMUXC_GPR3);
+	reg = __raw_readl(IOMUXC_GPR4);
+	reg |= IOMUXC_GPR4_VDOA_CACHE_EN | IOMUXC_GPR4_VPU_CACHE_EN |
+		IOMUXC_GPR4_IPU_CACHE_EN;
+	__raw_writel(reg, IOMUXC_GPR4);
+	__raw_writel(IOMUXC_GPR6_IPU1_QOS, IOMUXC_GPR6);
+	__raw_writel(IOMUXC_GPR7_IPU2_QOS, IOMUXC_GPR7);
+
 	num_cpu_idle_lock = 0x0;
 	if (cpu_is_mx6dl())
 		num_cpu_idle_lock = 0xffff0000;
diff --git a/arch/arm/mach-mx6/crm_regs.h b/arch/arm/mach-mx6/crm_regs.h
index 52fd75db9eb0..c99caad1e776 100644
--- a/arch/arm/mach-mx6/crm_regs.h
+++ b/arch/arm/mach-mx6/crm_regs.h
@@ -28,6 +28,13 @@
 #define IOMUXC_GPR12			(MXC_IOMUXC_BASE + 0x30)
 #define IOMUXC_GPR13			(MXC_IOMUXC_BASE + 0x34)
 
+#define IOMUXC_GPR3_OCRAM_CTL_EN	(0xf << 21)
+#define IOMUXC_GPR4_VDOA_CACHE_EN	(0xf << 28)
+#define IOMUXC_GPR4_VPU_CACHE_EN	(0xcc)
+#define IOMUXC_GPR4_IPU_CACHE_EN	(0x3)
+#define IOMUXC_GPR6_IPU1_QOS		(0x007f007f)
+#define IOMUXC_GPR7_IPU2_QOS		(0x007f007f)
+
 /* MMDC */
 #define MXC_MMDC_P0_BASE		MX6_IO_ADDRESS(MMDC_P0_BASE_ADDR)
 #define MMDC_MDMISC_OFFSET		(MXC_MMDC_P0_BASE + 0x18)
@@ -228,7 +235,7 @@
 /* Define the bits in register CBCDR */
 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK	(0x7 << 27)
 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET	(27)
-#define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL		(1 << 26)
+#define MXC_CCM_CBCDR_PERIPH2_CLK_SEL		(1 << 26)
 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL		(1 << 25)
 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK	(0x7 << 19)
 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET	(19)
@@ -255,7 +262,7 @@
 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET		(23)
 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK		(0x3 << 21)
 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET	(21)
-#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL		(1 << 20)
+#define MXC_CCM_CBCMR_PERIPH2_CLK2_SEL			(1 << 20)
 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK		(0x3 << 18)
 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET		(18)
 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK		(0x3 << 16)
diff --git a/arch/arm/mach-mx6/devices-imx6q.h b/arch/arm/mach-mx6/devices-imx6q.h
index 6ecc42c16965..3255cf79decf 100644
--- a/arch/arm/mach-mx6/devices-imx6q.h
+++ b/arch/arm/mach-mx6/devices-imx6q.h
@@ -242,3 +242,7 @@ extern const struct imx_pcie_data imx6q_pcie_data __initconst;
 #define imx6q_add_ion(id, pdata, size)	\
 	platform_device_register_resndata(NULL, "ion-mxc",\
 			id, NULL, 0, pdata, size);
+
+extern const struct imx_imx_keypad_data imx6sl_imx_keypad_data;
+#define imx6sl_add_imx_keypad(pdata)	\
+	imx_add_imx_keypad(&imx6sl_imx_keypad_data, pdata)
diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c
index a55b3fbfb94a..43d33376b52d 100755
--- a/arch/arm/plat-mxc/clock.c
+++ b/arch/arm/plat-mxc/clock.c
@@ -209,37 +209,6 @@ int clk_get_usecount(struct clk *clk)
 
 EXPORT_SYMBOL(clk_get_usecount);
 
-/*!
- * @brief Function to update the usage count for the requested clock.
- *
- * This function returns none.
- *
- * @param clk 	clk we want to update.
- * @param flag 	Increase or decrease usecount.
- *
- * @return Returns none.
- */
-void update_usecount(struct clk *clk, bool flag)
-{
-	if (!flag) {
-		if (clk_get_usecount(clk) > 1) {
-			mutex_lock(&clocks_mutex);
-			clk->usecount--;
-			mutex_unlock(&clocks_mutex);
-		} else
-			clk_disable(clk);
-	} else {
-		if (clk_get_usecount(clk) < 1)
-			clk_enable(clk);
-		else {
-			mutex_lock(&clocks_mutex);
-			clk->usecount++;
-			mutex_unlock(&clocks_mutex);
-		}
-	}
-}
-EXPORT_SYMBOL(update_usecount);
-
 /* Retrieve the *current* clock rate. If the clock itself
  * does not provide a special calculation routine, ask
  * its parent and so on, until one is able to return
diff --git a/arch/arm/plat-mxc/devices/platform-imx-keypad.c b/arch/arm/plat-mxc/devices/platform-imx-keypad.c
index 26366114b021..1a120218d05c 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-keypad.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-keypad.c
@@ -46,6 +46,11 @@ const struct imx_imx_keypad_data imx51_imx_keypad_data __initconst =
 	imx_imx_keypad_data_entry_single(MX51, SZ_16);
 #endif /* ifdef CONFIG_SOC_IMX51 */
 
+#ifdef CONFIG_SOC_IMX6SL
+const struct imx_imx_keypad_data imx6sl_imx_keypad_data __initconst =
+	imx_imx_keypad_data_entry_single(MX6SL, SZ_16);
+#endif /* ifdef CONFIG_SOC_IMX6SL */
+
 struct platform_device *__init imx_add_imx_keypad(
 		const struct imx_imx_keypad_data *data,
 		const struct matrix_keymap_data *pdata)
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx6sl.h b/arch/arm/plat-mxc/include/mach/iomux-mx6sl.h
index 5ce23184a540..3815e96f4b77 100755
--- a/arch/arm/plat-mxc/include/mach/iomux-mx6sl.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx6sl.h
@@ -69,6 +69,12 @@
 				PAD_CTL_PUE | PAD_CTL_PKE |		\
 				PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
 
+#define MX6SL_KEYPAD_CTRL	(PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
+				PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_120ohm)
+
+#define MX6SL_TSPAD_CTRL	(PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
+				PAD_CTL_PUS_47K_UP)
+
 #define MX6SL_PAD_AUD_MCLK__AUDMUX_AUDIO_CLK_OUT                              \
 		IOMUX_PAD(0x02A4, 0x004C, 0, 0x0000, 0, NO_PAD_CTRL)
 #define MX6SL_PAD_AUD_MCLK__PWM4_PWMO                                         \
@@ -1033,7 +1039,7 @@
 #define MX6SL_PAD_EPDC_PWRCTRL3__TCON_YDIODL                                  \
 		IOMUX_PAD(0x03E0, 0x00F0, 4, 0x0000, 0, NO_PAD_CTRL)
 #define MX6SL_PAD_EPDC_PWRCTRL3__GPIO_2_10                                    \
-		IOMUX_PAD(0x03E0, 0x00F0, 5, 0x0000, 0, NO_PAD_CTRL)
+		IOMUX_PAD(0x03E0, 0x00F0, 5, 0x0000, 0, MX6SL_TSPAD_CTRL)
 #define MX6SL_PAD_EPDC_PWRCTRL3__USDHC4_CD                                    \
 		IOMUX_PAD(0x03E0, 0x00F0, 6, 0x0854, 1, MX6SL_USDHC_PAD_CTRL)
 #define MX6SL_PAD_EPDC_PWRCTRL3__MMDC_MMDC_DEBUG_4                            \
@@ -1708,7 +1714,7 @@
 		IOMUX_PAD(0x0490, 0x0188, 7, 0x0000, 0, NO_PAD_CTRL)
 
 #define MX6SL_PAD_KEY_ROW0__KPP_ROW_0                                         \
-		IOMUX_PAD(0x0494, 0x018C, 0, 0x0754, 0, NO_PAD_CTRL)
+		IOMUX_PAD(0x0494, 0x018C, 0, 0x0754, 0, MX6SL_KEYPAD_CTRL)
 #define MX6SL_PAD_KEY_ROW0__I2C2_SDA                                          \
 		IOMUX_PAD(0x0494, 0x018C, 1 | IOMUX_CONFIG_SION, 0x0728, 2, MX6SL_I2C_PAD_CTRL)
 #define MX6SL_PAD_KEY_ROW0__LCDIF_DAT_1                                       \
@@ -1725,7 +1731,7 @@
 		IOMUX_PAD(0x0494, 0x018C, 7, 0x0000, 0, NO_PAD_CTRL)
 
 #define MX6SL_PAD_KEY_ROW1__KPP_ROW_1                                         \
-		IOMUX_PAD(0x0498, 0x0190, 0, 0x0758, 0, NO_PAD_CTRL)
+		IOMUX_PAD(0x0498, 0x0190, 0, 0x0758, 0, MX6SL_KEYPAD_CTRL)
 #define MX6SL_PAD_KEY_ROW1__ECSPI4_MISO                                       \
 		IOMUX_PAD(0x0498, 0x0190, 1, 0x06D4, 2, NO_PAD_CTRL)
 #define MX6SL_PAD_KEY_ROW1__LCDIF_DAT_3                                       \
@@ -1742,7 +1748,7 @@
 		IOMUX_PAD(0x0498, 0x0190, 7, 0x0000, 0, NO_PAD_CTRL)
 
 #define MX6SL_PAD_KEY_ROW2__KPP_ROW_2                                         \
-		IOMUX_PAD(0x049C, 0x0194, 0, 0x075C, 0, NO_PAD_CTRL)
+		IOMUX_PAD(0x049C, 0x0194, 0, 0x075C, 0, MX6SL_KEYPAD_CTRL)
 #define MX6SL_PAD_KEY_ROW2__ECSPI4_SCLK                                       \
 		IOMUX_PAD(0x049C, 0x0194, 1, 0x06D0, 2, NO_PAD_CTRL)
 #define MX6SL_PAD_KEY_ROW2__LCDIF_DAT_5                                       \
@@ -1759,7 +1765,7 @@
 		IOMUX_PAD(0x049C, 0x0194, 7, 0x0000, 0, NO_PAD_CTRL)
 
 #define MX6SL_PAD_KEY_ROW3__KPP_ROW_3                                         \
-		IOMUX_PAD(0x04A0, 0x0198, 0, 0x0760, 0, NO_PAD_CTRL)
+		IOMUX_PAD(0x04A0, 0x0198, 0, 0x0760, 0, MX6SL_KEYPAD_CTRL)
 #define MX6SL_PAD_KEY_ROW3__AUDMUX_AUD6_RXC                                   \
 		IOMUX_PAD(0x04A0, 0x0198, 1, 0x061C, 1, NO_PAD_CTRL)
 #define MX6SL_PAD_KEY_ROW3__LCDIF_DAT_7                                       \
diff --git a/arch/arm/plat-mxc/include/mach/mx6.h b/arch/arm/plat-mxc/include/mach/mx6.h
index 51c047acf8bc..bb4423e20063 100644
--- a/arch/arm/plat-mxc/include/mach/mx6.h
+++ b/arch/arm/plat-mxc/include/mach/mx6.h
@@ -178,7 +178,7 @@
 #define GPIO5_BASE_ADDR			(AIPS1_OFF_BASE_ADDR + 0x2C000)
 #define GPIO6_BASE_ADDR			(AIPS1_OFF_BASE_ADDR + 0x30000)
 #define GPIO7_BASE_ADDR			(AIPS1_OFF_BASE_ADDR + 0x34000)
-#define KPP_BASE_ADDR			(AIPS1_OFF_BASE_ADDR + 0x38000)
+#define MX6SL_KPP_BASE_ADDR		(AIPS1_OFF_BASE_ADDR + 0x38000)
 #define MX6Q_WDOG1_BASE_ADDR		(AIPS1_OFF_BASE_ADDR + 0x3C000)
 #define MX6Q_WDOG2_BASE_ADDR		(AIPS1_OFF_BASE_ADDR + 0x40000)
 #define CCM_BASE_ADDR			(AIPS1_OFF_BASE_ADDR + 0x44000)
@@ -418,6 +418,7 @@
 #define MXC_INT_WDOG1			112
 #define MXC_INT_WDOG2			113
 #define MXC_INT_KPP			114
+#define MX6SL_INT_KPP			114
 #define MX6Q_INT_PWM1			115
 #define MX6Q_INT_PWM2			116
 #define MX6Q_INT_PWM3			117