ENGR00262815-1 MX6SL-Add support for SDMA buffers in IRAM

Store SDMA channel and buffer descriptors in IRAM for MX6SL.
This will improve the audio playback power when both the
SDMA and audio buffers are all in IRAM. The DDR will be
self-refresh for longer periods of time.

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>

3 files changed, 11 insertions, 0 deletions

diff --git a/arch/arm/configs/imx6s_defconfig b/arch/arm/configs/imx6s_defconfig
index 17440cee6911..1cae0463855e 100644
--- a/arch/arm/configs/imx6s_defconfig
+++ b/arch/arm/configs/imx6s_defconfig
@@ -1,3 +1,4 @@
+
 #
 # Automatically generated make config: don't edit
 # Linux/arm 3.0.35 Kernel Configuration
@@ -316,6 +317,7 @@ CONFIG_MACH_MX6SL_EVK=y
 # CONFIG_MACH_MX6Q_SABRELITE is not set
 CONFIG_MACH_MX6Q_SABRESD=y
 # CONFIG_MACH_MX6Q_SABREAUTO is not set
+CONFIG_SDMA_IRAM=y
 
 #
 # MX6 Options:
diff --git a/arch/arm/mach-mx6/Kconfig b/arch/arm/mach-mx6/Kconfig
index faf68abba594..e567f67fa901 100644
--- a/arch/arm/mach-mx6/Kconfig
+++ b/arch/arm/mach-mx6/Kconfig
@@ -339,4 +339,11 @@ config MX6_ENET_IRQ_TO_GPIO
 	   Enabling this will direct all the ENET interrupts to a board specific GPIO.
 	   This will allow the system to enter WAIT mode when ENET is active.
 
+config SDMA_IRAM
+	bool "Use Internal RAM for SDMA data structures"
+	depends on IMX_SDMA && SOC_IMX6SL
+	help
+	  SDMA buffer or control structures are stored in the IRAM/OCRAM
+
+
 endif
diff --git a/arch/arm/mach-mx6/clock_mx6sl.c b/arch/arm/mach-mx6/clock_mx6sl.c
index 65ea38f6d872..fc42925d2a42 100755
--- a/arch/arm/mach-mx6/clock_mx6sl.c
+++ b/arch/arm/mach-mx6/clock_mx6sl.c
@@ -1701,6 +1701,7 @@ static struct clk mmdc_ch1_axi_clk[] = {
 	.secondary = &tzasc2_clk,
 	},
 };
+
 #if defined(CONFIG_SDMA_IRAM) || defined(CONFIG_SND_MXC_SOC_IRAM)
 static struct clk ocram_clk = {
 	__INIT_CLK_DEBUG(ocram_clk)
@@ -1712,6 +1713,7 @@ static struct clk ocram_clk = {
 	.disable = _clk_disable_inwait,
 };
 #endif
+
 static unsigned long _clk_ipg_perclk_get_rate(struct clk *clk)
 {
 	u32 reg, div;