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authorTony Prisk <linux@prisktech.co.nz>2013-05-10 17:35:11 +1200
committerTony Prisk <linux@prisktech.co.nz>2013-05-12 20:31:14 +1200
commit5c2b0a8531f594db82abc29e786b4c2d38fa298b (patch)
treef30bf9ade5b19ff378d9e5b52c681f43cbd806c3 /arch
parent7d4c6f3c5fdb216dfd36573d117eff602146cdcd (diff)
dts: vt8500: Populate missing PLL nodes
Add the missing devicetree nodes for PLL's found on the WM8505, WM8650 and WM8850 SoCs. Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boot/dts/wm8505.dtsi21
-rw-r--r--arch/arm/boot/dts/wm8650.dtsi21
-rw-r--r--arch/arm/boot/dts/wm8850.dtsi35
3 files changed, 77 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi
index 060b5fca2c16..702d866b6f57 100644
--- a/arch/arm/boot/dts/wm8505.dtsi
+++ b/arch/arm/boot/dts/wm8505.dtsi
@@ -81,6 +81,13 @@
clock-frequency = <25000000>;
};
+ plla: plla {
+ #clock-cells = <0>;
+ compatible = "via,vt8500-pll-clock";
+ clocks = <&ref25>;
+ reg = <0x200>;
+ };
+
pllb: pllb {
#clock-cells = <0>;
compatible = "via,vt8500-pll-clock";
@@ -88,6 +95,20 @@
reg = <0x204>;
};
+ pllc: pllc {
+ #clock-cells = <0>;
+ compatible = "via,vt8500-pll-clock";
+ clocks = <&ref25>;
+ reg = <0x208>;
+ };
+
+ plld: plld {
+ #clock-cells = <0>;
+ compatible = "via,vt8500-pll-clock";
+ clocks = <&ref25>;
+ reg = <0x20c>;
+ };
+
clkuart0: uart0 {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/wm8650.dtsi
index 4fdae5ce4dfb..46a4603c9c53 100644
--- a/arch/arm/boot/dts/wm8650.dtsi
+++ b/arch/arm/boot/dts/wm8650.dtsi
@@ -92,6 +92,27 @@
reg = <0x204>;
};
+ pllc: pllc {
+ #clock-cells = <0>;
+ compatible = "wm,wm8650-pll-clock";
+ clocks = <&ref25>;
+ reg = <0x208>;
+ };
+
+ plld: plld {
+ #clock-cells = <0>;
+ compatible = "wm,wm8650-pll-clock";
+ clocks = <&ref25>;
+ reg = <0x20c>;
+ };
+
+ plle: plle {
+ #clock-cells = <0>;
+ compatible = "wm,wm8650-pll-clock";
+ clocks = <&ref25>;
+ reg = <0x210>;
+ };
+
clkuart0: uart0 {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
diff --git a/arch/arm/boot/dts/wm8850.dtsi b/arch/arm/boot/dts/wm8850.dtsi
index 9239c0a3aeb7..59aaad98f544 100644
--- a/arch/arm/boot/dts/wm8850.dtsi
+++ b/arch/arm/boot/dts/wm8850.dtsi
@@ -95,6 +95,41 @@
reg = <0x204>;
};
+ pllc: pllc {
+ #clock-cells = <0>;
+ compatible = "wm,wm8850-pll-clock";
+ clocks = <&ref25>;
+ reg = <0x208>;
+ };
+
+ plld: plld {
+ #clock-cells = <0>;
+ compatible = "wm,wm8850-pll-clock";
+ clocks = <&ref25>;
+ reg = <0x20c>;
+ };
+
+ plle: plle {
+ #clock-cells = <0>;
+ compatible = "wm,wm8850-pll-clock";
+ clocks = <&ref25>;
+ reg = <0x210>;
+ };
+
+ pllf: pllf {
+ #clock-cells = <0>;
+ compatible = "wm,wm8850-pll-clock";
+ clocks = <&ref25>;
+ reg = <0x214>;
+ };
+
+ pllg: pllg {
+ #clock-cells = <0>;
+ compatible = "wm,wm8850-pll-clock";
+ clocks = <&ref25>;
+ reg = <0x218>;
+ };
+
clkuart0: uart0 {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";