diff options
| author | Olof Johansson <olof@lixom.net> | 2015-04-03 14:54:13 -0700 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2015-04-03 14:54:13 -0700 |
| commit | 4b3be93dd095af7488b0aee6e53c0e74a6130303 (patch) | |
| tree | 4dec2a7be6baeea03b9fc3c2c5ec4ef2a05d63a3 /arch | |
| parent | ccca5d7d0844f9d97a985dc159056cf6d2e5d9eb (diff) | |
| parent | 292a3546b9eb20bf5a292f4e55dd1a027424669f (diff) | |
Merge tag 'mvebu-dt-4.1-3' of git://git.infradead.org/linux-mvebu into next/dt
Merge "ARM: mvebu: dt changes for v4.1 (round 3)" from Gregory Clement:
mvebu dt changes for v4.1 (part #3)
These changes have no influence on the kernel behavior (except
removing a warning message), but they allow to have a better
representation of the hardware.
- conform L2CC node with ePAPR specification by adding cache-level
- remove cpuclk resources overlapping coredivclk registers on Armada XP
* tag 'mvebu-dt-4.1-3' of git://git.infradead.org/linux-mvebu:
ARM: mvebu: Conform L2CC node with ePAPR specification by adding cache-level
ARM: mvebu: clk: remove cpuclk resources overlapping coredivclk registers on Armada XP
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/armada-370.dtsi | 1 | ||||
| -rw-r--r-- | arch/arm/boot/dts/armada-xp.dtsi | 3 |
2 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index 50f259b20f94..00b50db57c9c 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -129,6 +129,7 @@ compatible = "marvell,aurora-outer-cache"; reg = <0x08000 0x1000>; cache-id-part = <0x100>; + cache-level = <2>; cache-unified; wt-override; }; diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index ff47345e19ed..013d63f69e36 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -79,6 +79,7 @@ compatible = "marvell,aurora-system-cache"; reg = <0x08000 0x1000>; cache-id-part = <0x100>; + cache-level = <2>; cache-unified; wt-override; }; @@ -150,7 +151,7 @@ cpuclk: clock-complex@18700 { #clock-cells = <1>; compatible = "marvell,armada-xp-cpu-clock"; - reg = <0x18700 0xA0>, <0x1c054 0x10>; + reg = <0x18700 0x24>, <0x1c054 0x10>; clocks = <&coreclk 1>; }; |