diff options
author | Matt Wagner <mwagner@nvidia.com> | 2013-06-11 16:14:43 -0700 |
---|---|---|
committer | Harshada Kale <hkale@nvidia.com> | 2013-07-26 01:42:19 -0700 |
commit | e0a560fa96a01fa3b10e0190fb82a94e9f1065c6 (patch) | |
tree | 66fe0afcc6723ac3e42491f1700a4ecdc39d0cd2 /arch | |
parent | 86e9dc464f0b4e47483c68532aa6a344dc9ce5c9 (diff) |
ARM: tegra11: dvfs: Update DVFS
Set CPU Vmin in DFLL mode 1.0V
Change the tune high voltage to 1050mV
Bug 1291764
Change-Id: I84a6854b0d7c85e602a6bc21d3fcb497613e5cae
Signed-off-by: Matt Wagner <mwagner@nvidia.com>
Reviewed-on: http://git-master/r/242586
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Tested-by: Sang-Hun Lee <sanlee@nvidia.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-tegra/tegra11_dvfs.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/mach-tegra/tegra11_dvfs.c b/arch/arm/mach-tegra/tegra11_dvfs.c index ceacee1badec..c8bfcb440aca 100644 --- a/arch/arm/mach-tegra/tegra11_dvfs.c +++ b/arch/arm/mach-tegra/tegra11_dvfs.c @@ -135,8 +135,8 @@ static struct cpu_cvb_dvfs cpu_cvb_dvfs_table[] = { .tune0_high_mv = 0x00b0009d, .tune1 = 0x0000001f, .droop_rate_min = 1000000, - .tune_high_min_millivolts = 1000, - .min_millivolts = 940, + .tune_high_min_millivolts = 1050, + .min_millivolts = 1000, }, .max_mv = 1350, .freqs_mult = KHZ, @@ -171,8 +171,8 @@ static struct cpu_cvb_dvfs cpu_cvb_dvfs_table[] = { .tune0_high_mv = 0x00b0009d, .tune1 = 0x0000001f, .droop_rate_min = 1000000, - .tune_high_min_millivolts = 1000, - .min_millivolts = 940, + .tune_high_min_millivolts = 1050, + .min_millivolts = 1000, }, .max_mv = 1350, .freqs_mult = KHZ, @@ -207,8 +207,8 @@ static struct cpu_cvb_dvfs cpu_cvb_dvfs_table[] = { .tune0_high_mv = 0x00b0009d, .tune1 = 0x0000001f, .droop_rate_min = 1000000, - .tune_high_min_millivolts = 1000, - .min_millivolts = 940, + .tune_high_min_millivolts = 1050, + .min_millivolts = 1000, }, .max_mv = 1350, .freqs_mult = KHZ, |