arm: tegra12: dvfs update for embedded SKU

CD575MI:
Max GPU freq is set to 852Mhz for 4/4/16
cpu_g powered by pllx is set to 1.5 and 1.8Ghz below 0 degC
Enable SOC dvfs for default personality
CD575M:
Lower CPU freq to 1912Mhz @ Max 1.12V
Lower GPU freq to 804Mhz @  Max 1.90V

Bug 1563635

Change-Id: Ib33f34fe2c0580d0f750de40f68560031f7266b0
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/711627
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

8 files changed, 1138 insertions, 115 deletions

diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index c886ee8f8eac..35f648fe57f2 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -107,7 +107,6 @@ config ARCH_TEGRA_12x_SOC
 	select TEGRA_ISOMGR
 	select TEGRA_ISOMGR_SYSFS
 	select PROC_DEVICETREE
-        select TEGRA_USE_SIMON
 	help
 	  Support for NVIDIA Tegra 12x family of SoCs, based upon the
 	  ARM Cortex-A15MP CPU
diff --git a/arch/arm/mach-tegra/board-ardbeg-memory.c b/arch/arm/mach-tegra/board-ardbeg-memory.c
index 4d1a7f812a48..04aa4419e942 100644
--- a/arch/arm/mach-tegra/board-ardbeg-memory.c
+++ b/arch/arm/mach-tegra/board-ardbeg-memory.c
@@ -18,6 +18,7 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/tegra-fuse.h>
 #include <linux/platform_data/tegra_emc_pdata.h>
 
 #include "board.h"
@@ -17518,6 +17519,917 @@ static struct tegra12_emc_table jetson_tk1_ddr3_emc_table[] = {
 	},
 };
 
+static struct tegra12_emc_table jetson_tk1_ddr3_embedded_emc_table[] = {
+	{
+		0x19,       /* V5.0.18 */
+		"01_204000_01_V5.0.18_V1.1", /* DVFS table version */
+		204000,     /* SDRAM frequency */
+		1050,        /* min voltage */
+		1050,        /* gpu min voltage */
+		"pllp_out0", /* clock source id */
+		0x40000002, /* CLK_SOURCE_EMC */
+		165,        /* number of burst_regs */
+		31,         /* number of up_down_regs */
+		{
+			0x00000009, /* EMC_RC */
+			0x00000035, /* EMC_RFC */
+			0x00000000, /* EMC_RFC_SLR */
+			0x00000006, /* EMC_RAS */
+			0x00000002, /* EMC_RP */
+			0x00000005, /* EMC_R2W */
+			0x0000000a, /* EMC_W2R */
+			0x00000005, /* EMC_R2P */
+			0x0000000b, /* EMC_W2P */
+			0x00000002, /* EMC_RD_RCD */
+			0x00000002, /* EMC_WR_RCD */
+			0x00000003, /* EMC_RRD */
+			0x00000003, /* EMC_REXT */
+			0x00000000, /* EMC_WEXT */
+			0x00000005, /* EMC_WDV */
+			0x00000005, /* EMC_WDV_MASK */
+			0x00000006, /* EMC_QUSE */
+			0x00000002, /* EMC_QUSE_WIDTH */
+			0x00000000, /* EMC_IBDLY */
+			0x00000004, /* EMC_EINPUT */
+			0x00000006, /* EMC_EINPUT_DURATION */
+			0x00010000, /* EMC_PUTERM_EXTRA */
+			0x00000003, /* EMC_PUTERM_WIDTH */
+			0x00000000, /* EMC_PUTERM_ADJ */
+			0x00000000, /* EMC_CDB_CNTL_1 */
+			0x00000000, /* EMC_CDB_CNTL_2 */
+			0x00000000, /* EMC_CDB_CNTL_3 */
+			0x00000003, /* EMC_QRST */
+			0x0000000d, /* EMC_QSAFE */
+			0x0000000f, /* EMC_RDV */
+			0x00000011, /* EMC_RDV_MASK */
+			0x00000607, /* EMC_REFRESH */
+			0x00000000, /* EMC_BURST_REFRESH_NUM */
+			0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000002, /* EMC_PDEX2WR */
+			0x00000002, /* EMC_PDEX2RD */
+			0x00000001, /* EMC_PCHG2PDEN */
+			0x00000000, /* EMC_ACT2PDEN */
+			0x00000032, /* EMC_AR2PDEN */
+			0x0000000f, /* EMC_RW2PDEN */
+			0x00000038, /* EMC_TXSR */
+			0x00000038, /* EMC_TXSRDLL */
+			0x00000004, /* EMC_TCKE */
+			0x00000005, /* EMC_TCKESR */
+			0x00000004, /* EMC_TPD */
+			0x00000006, /* EMC_TFAW */
+			0x00000000, /* EMC_TRPAB */
+			0x00000005, /* EMC_TCLKSTABLE */
+			0x00000005, /* EMC_TCLKSTOP */
+			0x00000638, /* EMC_TREFBW */
+			0x00000000, /* EMC_FBIO_CFG6 */
+			0x00000000, /* EMC_ODT_WRITE */
+			0x00000000, /* EMC_ODT_READ */
+			0x106aa298, /* EMC_FBIO_CFG5 */
+			0x002c00a0, /* EMC_CFG_DIG_DLL */
+			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+			0x00064000, /* EMC_DLL_XFORM_DQS0 */
+			0x00064000, /* EMC_DLL_XFORM_DQS1 */
+			0x00064000, /* EMC_DLL_XFORM_DQS2 */
+			0x00064000, /* EMC_DLL_XFORM_DQS3 */
+			0x00064000, /* EMC_DLL_XFORM_DQS4 */
+			0x00064000, /* EMC_DLL_XFORM_DQS5 */
+			0x00064000, /* EMC_DLL_XFORM_DQS6 */
+			0x00064000, /* EMC_DLL_XFORM_DQS7 */
+			0x00064000, /* EMC_DLL_XFORM_DQS8 */
+			0x00064000, /* EMC_DLL_XFORM_DQS9 */
+			0x00064000, /* EMC_DLL_XFORM_DQS10 */
+			0x00064000, /* EMC_DLL_XFORM_DQS11 */
+			0x00064000, /* EMC_DLL_XFORM_DQS12 */
+			0x00064000, /* EMC_DLL_XFORM_DQS13 */
+			0x00064000, /* EMC_DLL_XFORM_DQS14 */
+			0x00064000, /* EMC_DLL_XFORM_DQS15 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+			0x00018000, /* EMC_DLL_XFORM_ADDR2 */
+			0x00000000, /* EMC_DLL_XFORM_ADDR3 */
+			0x00000000, /* EMC_DLL_XFORM_ADDR4 */
+			0x00018000, /* EMC_DLL_XFORM_ADDR5 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE8 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE9 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE10 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE11 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE12 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE13 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE14 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE15 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS8 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS9 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS10 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS11 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS12 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
+			0x00070000, /* EMC_DLL_XFORM_DQ0 */
+			0x00070000, /* EMC_DLL_XFORM_DQ1 */
+			0x00070000, /* EMC_DLL_XFORM_DQ2 */
+			0x00070000, /* EMC_DLL_XFORM_DQ3 */
+			0x00007000, /* EMC_DLL_XFORM_DQ4 */
+			0x00007000, /* EMC_DLL_XFORM_DQ5 */
+			0x00007000, /* EMC_DLL_XFORM_DQ6 */
+			0x00007000, /* EMC_DLL_XFORM_DQ7 */
+			0x10000280, /* EMC_XM2CMDPADCTRL */
+			0x00000000, /* EMC_XM2CMDPADCTRL4 */
+			0x00111111, /* EMC_XM2CMDPADCTRL5 */
+			0x0130b118, /* EMC_XM2DQSPADCTRL2 */
+			0x00000000, /* EMC_XM2DQPADCTRL2 */
+			0x00000000, /* EMC_XM2DQPADCTRL3 */
+			0x77ffc081, /* EMC_XM2CLKPADCTRL */
+			0x00000606, /* EMC_XM2CLKPADCTRL2 */
+			0x81f1f108, /* EMC_XM2COMPPADCTRL */
+			0x07070004, /* EMC_XM2VTTGENPADCTRL */
+			0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
+			0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
+			0x51451400, /* EMC_XM2DQSPADCTRL3 */
+			0x00514514, /* EMC_XM2DQSPADCTRL4 */
+			0x00514514, /* EMC_XM2DQSPADCTRL5 */
+			0x51451400, /* EMC_XM2DQSPADCTRL6 */
+			0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+			0x00000066, /* EMC_TXDSRVTTGEN */
+			0x00000000, /* EMC_FBIO_SPARE */
+			0x00020000, /* EMC_ZCAL_INTERVAL */
+			0x00000100, /* EMC_ZCAL_WAIT_CNT */
+			0x000f000f, /* EMC_MRS_WAIT_CNT */
+			0x000f000f, /* EMC_MRS_WAIT_CNT2 */
+			0x00000000, /* EMC_CTT */
+			0x00000003, /* EMC_CTT_DURATION */
+			0x0000d2b3, /* EMC_CFG_PIPE */
+			0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */
+			0x0000000a, /* EMC_QPOP */
+			0x01000003, /* MC_EMEM_ARB_CFG */
+			0x80000040, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+			0x00000004, /* MC_EMEM_ARB_TIMING_RC */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RAS */
+			0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x00000003, /* MC_EMEM_ARB_TIMING_R2R */
+			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+			0x06040203, /* MC_EMEM_ARB_DA_TURNS */
+			0x000a0504, /* MC_EMEM_ARB_DA_COVERS */
+			0x73840a05, /* MC_EMEM_ARB_MISC0 */
+			0x70000f03, /* MC_EMEM_ARB_MISC1 */
+			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+		},
+		{
+			0x00000001, /* MC_MLL_MPCORER_PTSA_RATE */
+			0x00000062, /* MC_PTSA_GRANT_DECREMENT */
+			0x00ff006d, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
+			0x00ff006d, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
+			0x00ff003c, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
+			0x00ff00af, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
+			0x00ff004f, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
+			0x00ff00af, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
+			0x00ff004f, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
+			0x004e0049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
+			0x00ff0080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
+			0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
+			0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
+			0x00080057, /* MC_LATENCY_ALLOWANCE_HC_0 */
+			0x000000ff, /* MC_LATENCY_ALLOWANCE_HC_1 */
+			0x00ff0004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
+			0x00ff0063, /* MC_LATENCY_ALLOWANCE_GPU_0 */
+			0x00ff0036, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
+			0x00ff0024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
+			0x00ff006b, /* MC_LATENCY_ALLOWANCE_VIC_0 */
+			0x000000ff, /* MC_LATENCY_ALLOWANCE_VI2_0 */
+			0x00000050, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
+			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
+			0x00000050, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
+			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
+			0x00d400ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
+			0x00510050, /* MC_LATENCY_ALLOWANCE_VDE_1 */
+			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_2 */
+			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_3 */
+			0x00ff00c6, /* MC_LATENCY_ALLOWANCE_SATA_0 */
+			0x00ff006d, /* MC_LATENCY_ALLOWANCE_AFI_0 */
+		},
+		0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+		0x00000802, /* EMC_CTT_TERM_CTRL */
+		0x73240000, /* EMC_CFG */
+		0x000008cd, /* EMC_CFG_2 */
+		0x00040128, /* EMC_SEL_DPD_CTRL */
+		0x002c0068, /* EMC_CFG_DIG_DLL */
+		0x00000008, /* EMC_BGBIAS_CTL0 */
+		0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+		0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+		0xa1430000, /* EMC_AUTO_CAL_CONFIG */
+		0x80001221, /* Mode Register 0 */
+		0x80100003, /* Mode Register 1 */
+		0x80200008, /* Mode Register 2 */
+		0x00000000, /* Mode Register 4 */
+		3420,       /* expected dvfs latency (ns) */
+	},
+	{
+		0x19,       /* V5.0.18 */
+		"01_600000_01_V5.0.18_V1.1", /* DVFS table version */
+		600000,     /* SDRAM frequency */
+		1050,        /* min voltage */
+		1050,        /* gpu min voltage */
+		"pllc_ud",  /* clock source id */
+		0xe0000000, /* CLK_SOURCE_EMC */
+		165,        /* number of burst_regs */
+		31,         /* number of up_down_regs */
+		{
+			0x0000001b, /* EMC_RC */
+			0x0000009a, /* EMC_RFC */
+			0x00000000, /* EMC_RFC_SLR */
+			0x00000013, /* EMC_RAS */
+			0x00000007, /* EMC_RP */
+			0x00000007, /* EMC_R2W */
+			0x0000000b, /* EMC_W2R */
+			0x00000003, /* EMC_R2P */
+			0x00000010, /* EMC_W2P */
+			0x00000007, /* EMC_RD_RCD */
+			0x00000007, /* EMC_WR_RCD */
+			0x00000002, /* EMC_RRD */
+			0x00000002, /* EMC_REXT */
+			0x00000000, /* EMC_WEXT */
+			0x00000005, /* EMC_WDV */
+			0x00000005, /* EMC_WDV_MASK */
+			0x0000000a, /* EMC_QUSE */
+			0x00000002, /* EMC_QUSE_WIDTH */
+			0x00000000, /* EMC_IBDLY */
+			0x00000003, /* EMC_EINPUT */
+			0x0000000b, /* EMC_EINPUT_DURATION */
+			0x00070000, /* EMC_PUTERM_EXTRA */
+			0x00000003, /* EMC_PUTERM_WIDTH */
+			0x00000000, /* EMC_PUTERM_ADJ */
+			0x00000000, /* EMC_CDB_CNTL_1 */
+			0x00000000, /* EMC_CDB_CNTL_2 */
+			0x00000000, /* EMC_CDB_CNTL_3 */
+			0x00000002, /* EMC_QRST */
+			0x00000012, /* EMC_QSAFE */
+			0x00000016, /* EMC_RDV */
+			0x00000018, /* EMC_RDV_MASK */
+			0x00001208, /* EMC_REFRESH */
+			0x00000000, /* EMC_BURST_REFRESH_NUM */
+			0x00000482, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000002, /* EMC_PDEX2WR */
+			0x0000000d, /* EMC_PDEX2RD */
+			0x00000001, /* EMC_PCHG2PDEN */
+			0x00000000, /* EMC_ACT2PDEN */
+			0x00000096, /* EMC_AR2PDEN */
+			0x00000015, /* EMC_RW2PDEN */
+			0x000000a2, /* EMC_TXSR */
+			0x00000200, /* EMC_TXSRDLL */
+			0x00000004, /* EMC_TCKE */
+			0x00000005, /* EMC_TCKESR */
+			0x00000004, /* EMC_TPD */
+			0x00000013, /* EMC_TFAW */
+			0x00000000, /* EMC_TRPAB */
+			0x00000006, /* EMC_TCLKSTABLE */
+			0x00000006, /* EMC_TCLKSTOP */
+			0x00001248, /* EMC_TREFBW */
+			0x00000000, /* EMC_FBIO_CFG6 */
+			0x00000000, /* EMC_ODT_WRITE */
+			0x00000000, /* EMC_ODT_READ */
+			0x104ab098, /* EMC_FBIO_CFG5 */
+			0xe00e00b1, /* EMC_CFG_DIG_DLL */
+			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+			0x00000008, /* EMC_DLL_XFORM_DQS0 */
+			0x00000008, /* EMC_DLL_XFORM_DQS1 */
+			0x00000008, /* EMC_DLL_XFORM_DQS2 */
+			0x00000008, /* EMC_DLL_XFORM_DQS3 */
+			0x00000008, /* EMC_DLL_XFORM_DQS4 */
+			0x00000008, /* EMC_DLL_XFORM_DQS5 */
+			0x00000008, /* EMC_DLL_XFORM_DQS6 */
+			0x00000008, /* EMC_DLL_XFORM_DQS7 */
+			0x00000008, /* EMC_DLL_XFORM_DQS8 */
+			0x00000008, /* EMC_DLL_XFORM_DQS9 */
+			0x00000008, /* EMC_DLL_XFORM_DQS10 */
+			0x00000008, /* EMC_DLL_XFORM_DQS11 */
+			0x00000008, /* EMC_DLL_XFORM_DQS12 */
+			0x00000008, /* EMC_DLL_XFORM_DQS13 */
+			0x00000008, /* EMC_DLL_XFORM_DQS14 */
+			0x00000008, /* EMC_DLL_XFORM_DQS15 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+			0x0003c000, /* EMC_DLL_XFORM_ADDR0 */
+			0x0003c000, /* EMC_DLL_XFORM_ADDR1 */
+			0x00004000, /* EMC_DLL_XFORM_ADDR2 */
+			0x0003c000, /* EMC_DLL_XFORM_ADDR3 */
+			0x0003c000, /* EMC_DLL_XFORM_ADDR4 */
+			0x00004000, /* EMC_DLL_XFORM_ADDR5 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE8 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE9 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE10 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE11 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE12 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE13 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE14 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE15 */
+			0x00000002, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000003, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000003, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000002, /* EMC_DLI_TRIM_TXDQS4 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+			0x00000003, /* EMC_DLI_TRIM_TXDQS6 */
+			0x00000003, /* EMC_DLI_TRIM_TXDQS7 */
+			0x00000002, /* EMC_DLI_TRIM_TXDQS8 */
+			0x00000003, /* EMC_DLI_TRIM_TXDQS9 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS10 */
+			0x00000003, /* EMC_DLI_TRIM_TXDQS11 */
+			0x00000002, /* EMC_DLI_TRIM_TXDQS12 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
+			0x00000003, /* EMC_DLI_TRIM_TXDQS14 */
+			0x00000003, /* EMC_DLI_TRIM_TXDQS15 */
+			0x0000000c, /* EMC_DLL_XFORM_DQ0 */
+			0x0000000c, /* EMC_DLL_XFORM_DQ1 */
+			0x0000000c, /* EMC_DLL_XFORM_DQ2 */
+			0x0000000c, /* EMC_DLL_XFORM_DQ3 */
+			0x0000000c, /* EMC_DLL_XFORM_DQ4 */
+			0x0000000c, /* EMC_DLL_XFORM_DQ5 */
+			0x0000000c, /* EMC_DLL_XFORM_DQ6 */
+			0x0000000c, /* EMC_DLL_XFORM_DQ7 */
+			0x100002a0, /* EMC_XM2CMDPADCTRL */
+			0x00000000, /* EMC_XM2CMDPADCTRL4 */
+			0x00111111, /* EMC_XM2CMDPADCTRL5 */
+			0x0121113d, /* EMC_XM2DQSPADCTRL2 */
+			0x00000000, /* EMC_XM2DQPADCTRL2 */
+			0x00000000, /* EMC_XM2DQPADCTRL3 */
+			0x77ffc085, /* EMC_XM2CLKPADCTRL */
+			0x00000000, /* EMC_XM2CLKPADCTRL2 */
+			0x81f1f108, /* EMC_XM2COMPPADCTRL */
+			0x07070004, /* EMC_XM2VTTGENPADCTRL */
+			0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+			0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
+			0x51451420, /* EMC_XM2DQSPADCTRL3 */
+			0x00514514, /* EMC_XM2DQSPADCTRL4 */
+			0x00514514, /* EMC_XM2DQSPADCTRL5 */
+			0x51451400, /* EMC_XM2DQSPADCTRL6 */
+			0x0606003f, /* EMC_DSR_VTTGEN_DRV */
+			0x00000000, /* EMC_TXDSRVTTGEN */
+			0x00000000, /* EMC_FBIO_SPARE */
+			0x00020000, /* EMC_ZCAL_INTERVAL */
+			0x00000100, /* EMC_ZCAL_WAIT_CNT */
+			0x0128000f, /* EMC_MRS_WAIT_CNT */
+			0x0128000f, /* EMC_MRS_WAIT_CNT2 */
+			0x00000000, /* EMC_CTT */
+			0x00000003, /* EMC_CTT_DURATION */
+			0x000040a0, /* EMC_CFG_PIPE */
+			0x800024aa, /* EMC_DYN_SELF_REF_CONTROL */
+			0x0000000e, /* EMC_QPOP */
+			0x00000009, /* MC_EMEM_ARB_CFG */
+			0x80000040, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000003, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000004, /* MC_EMEM_ARB_TIMING_RP */
+			0x0000000e, /* MC_EMEM_ARB_TIMING_RC */
+			0x00000009, /* MC_EMEM_ARB_TIMING_RAS */
+			0x0000000a, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x0000000b, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000005, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000007, /* MC_EMEM_ARB_TIMING_W2R */
+			0x07050202, /* MC_EMEM_ARB_DA_TURNS */
+			0x00130b0e, /* MC_EMEM_ARB_DA_COVERS */
+			0x73a91b0f, /* MC_EMEM_ARB_MISC0 */
+			0x70000f03, /* MC_EMEM_ARB_MISC1 */
+			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+		},
+		{
+			0x0000000f, /* MC_MLL_MPCORER_PTSA_RATE */
+			0x00000120, /* MC_PTSA_GRANT_DECREMENT */
+			0x00aa0038, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
+			0x00aa0038, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
+			0x00aa003c, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
+			0x00aa0090, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
+			0x00aa0041, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
+			0x00aa0090, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
+			0x00aa0041, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
+			0x00270049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
+			0x00aa0080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
+			0x00aa0004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
+			0x00aa0004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
+			0x0008001d, /* MC_LATENCY_ALLOWANCE_HC_0 */
+			0x000000aa, /* MC_LATENCY_ALLOWANCE_HC_1 */
+			0x00aa0004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
+			0x00aa0022, /* MC_LATENCY_ALLOWANCE_GPU_0 */
+			0x00aa0018, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
+			0x00aa0024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
+			0x00aa0024, /* MC_LATENCY_ALLOWANCE_VIC_0 */
+			0x000000aa, /* MC_LATENCY_ALLOWANCE_VI2_0 */
+			0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
+			0x00aa00aa, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
+			0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
+			0x00aa00aa, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
+			0x00d400ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
+			0x00510029, /* MC_LATENCY_ALLOWANCE_VDE_1 */
+			0x00aa00aa, /* MC_LATENCY_ALLOWANCE_VDE_2 */
+			0x00aa00aa, /* MC_LATENCY_ALLOWANCE_VDE_3 */
+			0x00aa0065, /* MC_LATENCY_ALLOWANCE_SATA_0 */
+			0x00aa0025, /* MC_LATENCY_ALLOWANCE_AFI_0 */
+		},
+		0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+		0x00000802, /* EMC_CTT_TERM_CTRL */
+		0x73300000, /* EMC_CFG */
+		0x0000089d, /* EMC_CFG_2 */
+		0x00040008, /* EMC_SEL_DPD_CTRL */
+		0xe00e0069, /* EMC_CFG_DIG_DLL */
+		0x00000000, /* EMC_BGBIAS_CTL0 */
+		0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+		0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+		0xa1430000, /* EMC_AUTO_CAL_CONFIG */
+		0x80000b61, /* Mode Register 0 */
+		0x80100002, /* Mode Register 1 */
+		0x80200010, /* Mode Register 2 */
+		0x00000000, /* Mode Register 4 */
+		1440,       /* expected dvfs latency (ns) */
+	},
+	{
+		0x19,       /* V5.0.18 */
+		"01_792000_01_V5.0.18_V1.1", /* DVFS table version */
+		792000,     /* SDRAM frequency */
+		1050,        /* min voltage */
+		1050,        /* gpu min voltage */
+		"pllm_ud",  /* clock source id */
+		0x80000000, /* CLK_SOURCE_EMC */
+		165,        /* number of burst_regs */
+		31,         /* number of up_down_regs */
+		{
+			0x00000024, /* EMC_RC */
+			0x000000cc, /* EMC_RFC */
+			0x00000000, /* EMC_RFC_SLR */
+			0x00000019, /* EMC_RAS */
+			0x0000000a, /* EMC_RP */
+			0x00000008, /* EMC_R2W */
+			0x0000000d, /* EMC_W2R */
+			0x00000004, /* EMC_R2P */
+			0x00000013, /* EMC_W2P */
+			0x0000000a, /* EMC_RD_RCD */
+			0x0000000a, /* EMC_WR_RCD */
+			0x00000004, /* EMC_RRD */
+			0x00000002, /* EMC_REXT */
+			0x00000000, /* EMC_WEXT */
+			0x00000006, /* EMC_WDV */
+			0x00000006, /* EMC_WDV_MASK */
+			0x0000000b, /* EMC_QUSE */
+			0x00000002, /* EMC_QUSE_WIDTH */
+			0x00000000, /* EMC_IBDLY */
+			0x00000002, /* EMC_EINPUT */
+			0x0000000d, /* EMC_EINPUT_DURATION */
+			0x00080000, /* EMC_PUTERM_EXTRA */
+			0x00000004, /* EMC_PUTERM_WIDTH */
+			0x00000000, /* EMC_PUTERM_ADJ */
+			0x00000000, /* EMC_CDB_CNTL_1 */
+			0x00000000, /* EMC_CDB_CNTL_2 */
+			0x00000000, /* EMC_CDB_CNTL_3 */
+			0x00000001, /* EMC_QRST */
+			0x00000014, /* EMC_QSAFE */
+			0x00000018, /* EMC_RDV */
+			0x0000001a, /* EMC_RDV_MASK */
+			0x000017e2, /* EMC_REFRESH */
+			0x00000000, /* EMC_BURST_REFRESH_NUM */
+			0x000005f8, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000003, /* EMC_PDEX2WR */
+			0x00000011, /* EMC_PDEX2RD */
+			0x00000001, /* EMC_PCHG2PDEN */
+			0x00000000, /* EMC_ACT2PDEN */
+			0x000000c6, /* EMC_AR2PDEN */
+			0x00000018, /* EMC_RW2PDEN */
+			0x000000d6, /* EMC_TXSR */
+			0x00000200, /* EMC_TXSRDLL */
+			0x00000005, /* EMC_TCKE */
+			0x00000006, /* EMC_TCKESR */
+			0x00000005, /* EMC_TPD */
+			0x00000019, /* EMC_TFAW */
+			0x00000000, /* EMC_TRPAB */
+			0x00000008, /* EMC_TCLKSTABLE */
+			0x00000008, /* EMC_TCLKSTOP */
+			0x00001822, /* EMC_TREFBW */
+			0x00000000, /* EMC_FBIO_CFG6 */
+			0x00000000, /* EMC_ODT_WRITE */
+			0x00000000, /* EMC_ODT_READ */
+			0x104ab098, /* EMC_FBIO_CFG5 */
+			0xe00700b1, /* EMC_CFG_DIG_DLL */
+			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+			0x00000008, /* EMC_DLL_XFORM_DQS0 */
+			0x00000008, /* EMC_DLL_XFORM_DQS1 */
+			0x00000008, /* EMC_DLL_XFORM_DQS2 */
+			0x007fc008, /* EMC_DLL_XFORM_DQS3 */
+			0x00000008, /* EMC_DLL_XFORM_DQS4 */
+			0x00000008, /* EMC_DLL_XFORM_DQS5 */
+			0x00000008, /* EMC_DLL_XFORM_DQS6 */
+			0x00000008, /* EMC_DLL_XFORM_DQS7 */
+			0x00000008, /* EMC_DLL_XFORM_DQS8 */
+			0x00000008, /* EMC_DLL_XFORM_DQS9 */
+			0x00000008, /* EMC_DLL_XFORM_DQS10 */
+			0x00000008, /* EMC_DLL_XFORM_DQS11 */
+			0x00000008, /* EMC_DLL_XFORM_DQS12 */
+			0x00000008, /* EMC_DLL_XFORM_DQS13 */
+			0x00000008, /* EMC_DLL_XFORM_DQS14 */
+			0x00000008, /* EMC_DLL_XFORM_DQS15 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+			0x00028000, /* EMC_DLL_XFORM_ADDR0 */
+			0x00028000, /* EMC_DLL_XFORM_ADDR1 */
+			0x00004000, /* EMC_DLL_XFORM_ADDR2 */
+			0x00028000, /* EMC_DLL_XFORM_ADDR3 */
+			0x00028000, /* EMC_DLL_XFORM_ADDR4 */
+			0x00004000, /* EMC_DLL_XFORM_ADDR5 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE8 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE9 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE10 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE11 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE12 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE13 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE14 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE15 */
+			0x00000006, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000007, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000004, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000006, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000006, /* EMC_DLI_TRIM_TXDQS4 */
+			0x00000003, /* EMC_DLI_TRIM_TXDQS5 */
+			0x00000006, /* EMC_DLI_TRIM_TXDQS6 */
+			0x00000007, /* EMC_DLI_TRIM_TXDQS7 */
+			0x00000006, /* EMC_DLI_TRIM_TXDQS8 */
+			0x00000007, /* EMC_DLI_TRIM_TXDQS9 */
+			0x00000004, /* EMC_DLI_TRIM_TXDQS10 */
+			0x00000006, /* EMC_DLI_TRIM_TXDQS11 */
+			0x00000006, /* EMC_DLI_TRIM_TXDQS12 */
+			0x00000003, /* EMC_DLI_TRIM_TXDQS13 */
+			0x00000006, /* EMC_DLI_TRIM_TXDQS14 */
+			0x00000007, /* EMC_DLI_TRIM_TXDQS15 */
+			0x00000008, /* EMC_DLL_XFORM_DQ0 */
+			0x00000008, /* EMC_DLL_XFORM_DQ1 */
+			0x00000008, /* EMC_DLL_XFORM_DQ2 */
+			0x00000008, /* EMC_DLL_XFORM_DQ3 */
+			0x00000008, /* EMC_DLL_XFORM_DQ4 */
+			0x00000008, /* EMC_DLL_XFORM_DQ5 */
+			0x00000008, /* EMC_DLL_XFORM_DQ6 */
+			0x00000008, /* EMC_DLL_XFORM_DQ7 */
+			0x100002a0, /* EMC_XM2CMDPADCTRL */
+			0x00000000, /* EMC_XM2CMDPADCTRL4 */
+			0x00111111, /* EMC_XM2CMDPADCTRL5 */
+			0x0120113d, /* EMC_XM2DQSPADCTRL2 */
+			0x00000000, /* EMC_XM2DQPADCTRL2 */
+			0x00000000, /* EMC_XM2DQPADCTRL3 */
+			0x77ffc085, /* EMC_XM2CLKPADCTRL */
+			0x00000000, /* EMC_XM2CLKPADCTRL2 */
+			0x81f1f108, /* EMC_XM2COMPPADCTRL */
+			0x07070004, /* EMC_XM2VTTGENPADCTRL */
+			0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+			0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
+			0x51451420, /* EMC_XM2DQSPADCTRL3 */
+			0x00514514, /* EMC_XM2DQSPADCTRL4 */
+			0x00514514, /* EMC_XM2DQSPADCTRL5 */
+			0x51451400, /* EMC_XM2DQSPADCTRL6 */
+			0x0606003f, /* EMC_DSR_VTTGEN_DRV */
+			0x00000000, /* EMC_TXDSRVTTGEN */
+			0x00000000, /* EMC_FBIO_SPARE */
+			0x00020000, /* EMC_ZCAL_INTERVAL */
+			0x00000100, /* EMC_ZCAL_WAIT_CNT */
+			0x00f8000f, /* EMC_MRS_WAIT_CNT */
+			0x00f8000f, /* EMC_MRS_WAIT_CNT2 */
+			0x00000000, /* EMC_CTT */
+			0x00000004, /* EMC_CTT_DURATION */
+			0x00004080, /* EMC_CFG_PIPE */
+			0x80003012, /* EMC_DYN_SELF_REF_CONTROL */
+			0x0000000f, /* EMC_QPOP */
+			0x0e00000b, /* MC_EMEM_ARB_CFG */
+			0x80000040, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000005, /* MC_EMEM_ARB_TIMING_RP */
+			0x00000013, /* MC_EMEM_ARB_TIMING_RC */
+			0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */
+			0x0000000d, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000006, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
+			0x08060202, /* MC_EMEM_ARB_DA_TURNS */
+			0x00170e13, /* MC_EMEM_ARB_DA_COVERS */
+			0x734c2414, /* MC_EMEM_ARB_MISC0 */
+			0x70000f02, /* MC_EMEM_ARB_MISC1 */
+			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+		},
+		{
+			0x00000013, /* MC_MLL_MPCORER_PTSA_RATE */
+			0x0000017c, /* MC_PTSA_GRANT_DECREMENT */
+			0x00810038, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
+			0x00810038, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
+			0x0081003c, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
+			0x00810090, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
+			0x00810041, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
+			0x00810090, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
+			0x00810041, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
+			0x00270049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
+			0x00810080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
+			0x00810004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
+			0x00810004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
+			0x00080016, /* MC_LATENCY_ALLOWANCE_HC_0 */
+			0x00000081, /* MC_LATENCY_ALLOWANCE_HC_1 */
+			0x00810004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
+			0x00810019, /* MC_LATENCY_ALLOWANCE_GPU_0 */
+			0x00810018, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
+			0x00810024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
+			0x0081001c, /* MC_LATENCY_ALLOWANCE_VIC_0 */
+			0x00000081, /* MC_LATENCY_ALLOWANCE_VI2_0 */
+			0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
+			0x00810081, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
+			0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
+			0x00810081, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
+			0x00d400ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
+			0x00510029, /* MC_LATENCY_ALLOWANCE_VDE_1 */
+			0x00810081, /* MC_LATENCY_ALLOWANCE_VDE_2 */
+			0x00810081, /* MC_LATENCY_ALLOWANCE_VDE_3 */
+			0x00810065, /* MC_LATENCY_ALLOWANCE_SATA_0 */
+			0x0081001c, /* MC_LATENCY_ALLOWANCE_AFI_0 */
+		},
+		0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+		0x00000802, /* EMC_CTT_TERM_CTRL */
+		0x73300000, /* EMC_CFG */
+		0x0000089d, /* EMC_CFG_2 */
+		0x00040000, /* EMC_SEL_DPD_CTRL */
+		0xe0070069, /* EMC_CFG_DIG_DLL */
+		0x00000000, /* EMC_BGBIAS_CTL0 */
+		0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+		0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+		0xa1430000, /* EMC_AUTO_CAL_CONFIG */
+		0x80000d71, /* Mode Register 0 */
+		0x80100002, /* Mode Register 1 */
+		0x80200018, /* Mode Register 2 */
+		0x00000000, /* Mode Register 4 */
+		1200,       /* expected dvfs latency (ns) */
+	},
+	{
+		0x19,       /* V5.0.18 */
+		"01_924000_01_V5.0.18_V1.1", /* DVFS table version */
+		924000,     /* SDRAM frequency */
+		1100,       /* min voltage */
+		1100,       /* gpu min voltage */
+		"pllm_ud",  /* clock source id */
+		0x80000000, /* CLK_SOURCE_EMC */
+		165,        /* number of burst_regs */
+		31,         /* number of up_down_regs */
+		{
+			0x0000002b, /* EMC_RC */
+			0x000000ef, /* EMC_RFC */
+			0x00000000, /* EMC_RFC_SLR */
+			0x0000001e, /* EMC_RAS */
+			0x0000000b, /* EMC_RP */
+			0x00000009, /* EMC_R2W */
+			0x0000000f, /* EMC_W2R */
+			0x00000005, /* EMC_R2P */
+			0x00000016, /* EMC_W2P */
+			0x0000000b, /* EMC_RD_RCD */
+			0x0000000b, /* EMC_WR_RCD */
+			0x00000004, /* EMC_RRD */
+			0x00000002, /* EMC_REXT */
+			0x00000000, /* EMC_WEXT */
+			0x00000007, /* EMC_WDV */
+			0x00000007, /* EMC_WDV_MASK */
+			0x0000000d, /* EMC_QUSE */
+			0x00000002, /* EMC_QUSE_WIDTH */
+			0x00000000, /* EMC_IBDLY */
+			0x00000002, /* EMC_EINPUT */
+			0x0000000f, /* EMC_EINPUT_DURATION */
+			0x000a0000, /* EMC_PUTERM_EXTRA */
+			0x00000004, /* EMC_PUTERM_WIDTH */
+			0x00000000, /* EMC_PUTERM_ADJ */
+			0x00000000, /* EMC_CDB_CNTL_1 */
+			0x00000000, /* EMC_CDB_CNTL_2 */
+			0x00000000, /* EMC_CDB_CNTL_3 */
+			0x00000001, /* EMC_QRST */
+			0x00000016, /* EMC_QSAFE */
+			0x0000001a, /* EMC_RDV */
+			0x0000001c, /* EMC_RDV_MASK */
+			0x00001be7, /* EMC_REFRESH */
+			0x00000000, /* EMC_BURST_REFRESH_NUM */
+			0x000006f9, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000004, /* EMC_PDEX2WR */
+			0x00000015, /* EMC_PDEX2RD */
+			0x00000001, /* EMC_PCHG2PDEN */
+			0x00000000, /* EMC_ACT2PDEN */
+			0x000000e6, /* EMC_AR2PDEN */
+			0x0000001b, /* EMC_RW2PDEN */
+			0x000000fa, /* EMC_TXSR */
+			0x00000200, /* EMC_TXSRDLL */
+			0x00000006, /* EMC_TCKE */
+			0x00000007, /* EMC_TCKESR */
+			0x00000006, /* EMC_TPD */
+			0x0000001e, /* EMC_TFAW */
+			0x00000000, /* EMC_TRPAB */
+			0x0000000a, /* EMC_TCLKSTABLE */
+			0x0000000a, /* EMC_TCLKSTOP */
+			0x00001c28, /* EMC_TREFBW */
+			0x00000000, /* EMC_FBIO_CFG6 */
+			0x00000000, /* EMC_ODT_WRITE */
+			0x00000000, /* EMC_ODT_READ */
+			0x104ab898, /* EMC_FBIO_CFG5 */
+			0xe00400b1, /* EMC_CFG_DIG_DLL */
+			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+			0x007fc008, /* EMC_DLL_XFORM_DQS0 */
+			0x007fc008, /* EMC_DLL_XFORM_DQS1 */
+			0x007fc008, /* EMC_DLL_XFORM_DQS2 */
+			0x007fc008, /* EMC_DLL_XFORM_DQS3 */
+			0x007fc008, /* EMC_DLL_XFORM_DQS4 */
+			0x007fc008, /* EMC_DLL_XFORM_DQS5 */
+			0x007fc008, /* EMC_DLL_XFORM_DQS6 */
+			0x007fc008, /* EMC_DLL_XFORM_DQS7 */
+			0x007fc008, /* EMC_DLL_XFORM_DQS8 */
+			0x007fc008, /* EMC_DLL_XFORM_DQS9 */
+			0x007fc008, /* EMC_DLL_XFORM_DQS10 */
+			0x007fc008, /* EMC_DLL_XFORM_DQS11 */
+			0x007fc008, /* EMC_DLL_XFORM_DQS12 */
+			0x007fc008, /* EMC_DLL_XFORM_DQS13 */
+			0x007fc008, /* EMC_DLL_XFORM_DQS14 */
+			0x007fc008, /* EMC_DLL_XFORM_DQS15 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+			0x0002c000, /* EMC_DLL_XFORM_ADDR0 */
+			0x0002c000, /* EMC_DLL_XFORM_ADDR1 */
+			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+			0x0002c000, /* EMC_DLL_XFORM_ADDR3 */
+			0x0002c000, /* EMC_DLL_XFORM_ADDR4 */
+			0x00000000, /* EMC_DLL_XFORM_ADDR5 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE8 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE9 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE10 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE11 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE12 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE13 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE14 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE15 */
+			0x00000005, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000005, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000005, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000005, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000005, /* EMC_DLI_TRIM_TXDQS4 */
+			0x00000005, /* EMC_DLI_TRIM_TXDQS5 */
+			0x00000005, /* EMC_DLI_TRIM_TXDQS6 */
+			0x00000005, /* EMC_DLI_TRIM_TXDQS7 */
+			0x00000005, /* EMC_DLI_TRIM_TXDQS8 */
+			0x00000005, /* EMC_DLI_TRIM_TXDQS9 */
+			0x00000005, /* EMC_DLI_TRIM_TXDQS10 */
+			0x00000005, /* EMC_DLI_TRIM_TXDQS11 */
+			0x00000005, /* EMC_DLI_TRIM_TXDQS12 */
+			0x00000005, /* EMC_DLI_TRIM_TXDQS13 */
+			0x00000005, /* EMC_DLI_TRIM_TXDQS14 */
+			0x00000005, /* EMC_DLI_TRIM_TXDQS15 */
+			0x00000008, /* EMC_DLL_XFORM_DQ0 */
+			0x00000008, /* EMC_DLL_XFORM_DQ1 */
+			0x00000008, /* EMC_DLL_XFORM_DQ2 */
+			0x00000008, /* EMC_DLL_XFORM_DQ3 */
+			0x00000008, /* EMC_DLL_XFORM_DQ4 */
+			0x00000008, /* EMC_DLL_XFORM_DQ5 */
+			0x00000008, /* EMC_DLL_XFORM_DQ6 */
+			0x00000008, /* EMC_DLL_XFORM_DQ7 */
+			0x100002a0, /* EMC_XM2CMDPADCTRL */
+			0x00000000, /* EMC_XM2CMDPADCTRL4 */
+			0x00111111, /* EMC_XM2CMDPADCTRL5 */
+			0x0120113d, /* EMC_XM2DQSPADCTRL2 */
+			0x00000000, /* EMC_XM2DQPADCTRL2 */
+			0x00000000, /* EMC_XM2DQPADCTRL3 */
+			0x77ffc085, /* EMC_XM2CLKPADCTRL */
+			0x00000000, /* EMC_XM2CLKPADCTRL2 */
+			0x81f1f108, /* EMC_XM2COMPPADCTRL */
+			0x07070004, /* EMC_XM2VTTGENPADCTRL */
+			0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+			0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
+			0x5d755520, /* EMC_XM2DQSPADCTRL3 */
+			0x00514514, /* EMC_XM2DQSPADCTRL4 */
+			0x00514514, /* EMC_XM2DQSPADCTRL5 */
+			0x5d555500, /* EMC_XM2DQSPADCTRL6 */
+			0x0606003f, /* EMC_DSR_VTTGEN_DRV */
+			0x00000000, /* EMC_TXDSRVTTGEN */
+			0x00000000, /* EMC_FBIO_SPARE */
+			0x00020000, /* EMC_ZCAL_INTERVAL */
+			0x00000128, /* EMC_ZCAL_WAIT_CNT */
+			0x00ce000f, /* EMC_MRS_WAIT_CNT */
+			0x00ce000f, /* EMC_MRS_WAIT_CNT2 */
+			0x00000000, /* EMC_CTT */
+			0x00000004, /* EMC_CTT_DURATION */
+			0x00004080, /* EMC_CFG_PIPE */
+			0x800037ea, /* EMC_DYN_SELF_REF_CONTROL */
+			0x00000011, /* EMC_QPOP */
+			0x0e00000d, /* MC_EMEM_ARB_CFG */
+			0x80000040, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000005, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000006, /* MC_EMEM_ARB_TIMING_RP */
+			0x00000016, /* MC_EMEM_ARB_TIMING_RC */
+			0x0000000e, /* MC_EMEM_ARB_TIMING_RAS */
+			0x0000000f, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000004, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x0000000e, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000006, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000009, /* MC_EMEM_ARB_TIMING_W2R */
+			0x09060202, /* MC_EMEM_ARB_DA_TURNS */
+			0x001a1016, /* MC_EMEM_ARB_DA_COVERS */
+			0x734e2a17, /* MC_EMEM_ARB_MISC0 */
+			0x70000f02, /* MC_EMEM_ARB_MISC1 */
+			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+		},
+		{
+			0x00000017, /* MC_MLL_MPCORER_PTSA_RATE */
+			0x000001bb, /* MC_PTSA_GRANT_DECREMENT */
+			0x006e0038, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
+			0x006e0038, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
+			0x006e003c, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
+			0x006e0090, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
+			0x006e0041, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
+			0x006e0090, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
+			0x006e0041, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
+			0x00270049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
+			0x006e0080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
+			0x006e0004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
+			0x006e0004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
+			0x00080016, /* MC_LATENCY_ALLOWANCE_HC_0 */
+			0x0000006e, /* MC_LATENCY_ALLOWANCE_HC_1 */
+			0x006e0004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
+			0x006e0019, /* MC_LATENCY_ALLOWANCE_GPU_0 */
+			0x006e0018, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
+			0x006e0024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
+			0x006e001b, /* MC_LATENCY_ALLOWANCE_VIC_0 */
+			0x0000006e, /* MC_LATENCY_ALLOWANCE_VI2_0 */
+			0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
+			0x006e006e, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
+			0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
+			0x006e006e, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
+			0x00d400ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
+			0x00510029, /* MC_LATENCY_ALLOWANCE_VDE_1 */
+			0x006e006e, /* MC_LATENCY_ALLOWANCE_VDE_2 */
+			0x006e006e, /* MC_LATENCY_ALLOWANCE_VDE_3 */
+			0x006e0065, /* MC_LATENCY_ALLOWANCE_SATA_0 */
+			0x006e001c, /* MC_LATENCY_ALLOWANCE_AFI_0 */
+		},
+		0x0000004c, /* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+		0x00000802, /* EMC_CTT_TERM_CTRL */
+		0x73300000, /* EMC_CFG */
+		0x0000089d, /* EMC_CFG_2 */
+		0x00040000, /* EMC_SEL_DPD_CTRL */
+		0xe0040069, /* EMC_CFG_DIG_DLL */
+		0x00000000, /* EMC_BGBIAS_CTL0 */
+		0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+		0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+		0xa1430606, /* EMC_AUTO_CAL_CONFIG */
+		0x80000f15, /* Mode Register 0 */
+		0x80100002, /* Mode Register 1 */
+		0x80200020, /* Mode Register 2 */
+		0x00000000, /* Mode Register 4 */
+		1180,       /* expected dvfs latency (ns) */
+	},
+};
+
 static struct tegra12_emc_table jetson_tk1_ddr3_4GB_emc_table[] = {
 
 	{
@@ -24615,6 +25527,12 @@ static struct tegra12_emc_pdata jetson_tk1_2GB_emc_pdata = {
 	.num_tables = ARRAY_SIZE(jetson_tk1_ddr3_emc_table),
 };
 
+static struct tegra12_emc_pdata jetson_tk1_2GB_embedded_emc_pdata = {
+	.description = "ardbeg_emc_tables",
+	.tables = jetson_tk1_ddr3_embedded_emc_table,
+	.num_tables = ARRAY_SIZE(jetson_tk1_ddr3_embedded_emc_table),
+};
+
 static struct tegra12_emc_pdata jetson_tk1_4GB_emc_pdata = {
 	.description = "ardbeg_emc_tables",
 	.tables = jetson_tk1_ddr3_4GB_emc_table,
@@ -24639,6 +25557,7 @@ static struct tegra12_emc_pdata jetson_tk1_PM377_4GB_emc_pdata = {
 int __init ardbeg_emc_init(void)
 {
 	struct board_info bi;
+	int soc_speedo_id = tegra_soc_speedo_id();
 
 	/* If Device Tree Partition contains emc-tables, load them */
 	if (of_find_compatible_node(NULL, NULL, "nvidia,tegra12-emc")) {
@@ -24686,9 +25605,15 @@ int __init ardbeg_emc_init(void)
 					tegra_emc_device.dev.platform_data =
 						&jetson_tk1_4GB_emc_pdata;
 				} else {
-					pr_info("Loading jetson TK1 EMC tables.\n");
-					tegra_emc_device.dev.platform_data =
-						&jetson_tk1_2GB_emc_pdata;
+					if (soc_speedo_id == 4) {
+						pr_info("Loading jetson TK1 EMC Embedded tables.\n");
+						tegra_emc_device.dev.platform_data =
+							&jetson_tk1_2GB_embedded_emc_pdata;
+					} else {
+						pr_info("Loading jetson TK1 EMC tables.\n");
+						tegra_emc_device.dev.platform_data =
+							&jetson_tk1_2GB_emc_pdata;
+					}
 				}
 			} else {
 				pr_info("Loading PM375 EMC tables.\n");
diff --git a/arch/arm/mach-tegra/board-ardbeg-power.c b/arch/arm/mach-tegra/board-ardbeg-power.c
index 684a950704db..a11cd6db4eed 100644
--- a/arch/arm/mach-tegra/board-ardbeg-power.c
+++ b/arch/arm/mach-tegra/board-ardbeg-power.c
@@ -406,7 +406,7 @@ int __init ardbeg_edp_init(void)
 	else if (pmu_board_info.board_id == BOARD_PM374)
 		regulator_mA = 16000;
 	else if (pmu_board_info.board_id == BOARD_PM375)
-		regulator_mA = 10500;
+		regulator_mA = 11400;
 	else
 		regulator_mA = 12000;
 
diff --git a/arch/arm/mach-tegra/board-ardbeg-sensors.c b/arch/arm/mach-tegra/board-ardbeg-sensors.c
index 9d621c0b708a..9915bf07152d 100644
--- a/arch/arm/mach-tegra/board-ardbeg-sensors.c
+++ b/arch/arm/mach-tegra/board-ardbeg-sensors.c
@@ -2074,7 +2074,8 @@ static int ardbeg_nct72_init(void)
 	}
 
 	/* vmin trips are bound to soctherm on norrin */
-	if (!(board_info.board_id == BOARD_PM374))
+	if (!(board_info.board_id == BOARD_PM374) &&
+		!(board_info.board_id == BOARD_PM375))
 		tegra_add_all_vmin_trips(ardbeg_nct72_pdata.sensors[EXT].trips,
 			&ardbeg_nct72_pdata.sensors[EXT].num_trips);
 
@@ -2103,8 +2104,8 @@ static int ardbeg_nct72_init(void)
 		ARRAY_SIZE(ardbeg_i2c_nct72_board_info));
 	else if (board_info.board_id == BOARD_PM375 ||
 			board_info.board_id == BOARD_PM377) {
-		ardbeg_nct72_pdata.sensors[EXT].shutdown_limit = 100;
-		ardbeg_nct72_pdata.sensors[LOC].shutdown_limit = 95;
+		ardbeg_nct72_pdata.sensors[EXT].shutdown_limit = 105;
+		ardbeg_nct72_pdata.sensors[LOC].shutdown_limit = 100;
 		i2c_register_board_info(0, ardbeg_i2c_nct72_board_info,
 					1); /* only register device[0] */
 	}
diff --git a/arch/arm/mach-tegra/dvfs.c b/arch/arm/mach-tegra/dvfs.c
index 61756532edb9..a87c6a75293a 100644
--- a/arch/arm/mach-tegra/dvfs.c
+++ b/arch/arm/mach-tegra/dvfs.c
@@ -956,7 +956,7 @@ static int dvfs_override_core_voltage(int override_mv)
 	floor = dvfs_rail_get_override_floor(rail);
 	ceiling = rail->nominal_millivolts;
 	if (override_mv && ((override_mv < floor) || (override_mv > ceiling))) {
-		pr_err("%s: override level %d outside the range [%d...%d]\n",
+		pr_info("%s: override level %d outside the range [%d...%d]\n",
 		       __func__, override_mv, floor, ceiling);
 		mutex_unlock(&rail_override_lock);
 		return -EINVAL;
diff --git a/arch/arm/mach-tegra/edp.c b/arch/arm/mach-tegra/edp.c
index 6ac0f3f7e578..4ff76efca9e1 100644
--- a/arch/arm/mach-tegra/edp.c
+++ b/arch/arm/mach-tegra/edp.c
@@ -469,7 +469,11 @@ static int init_cpu_edp_limits_calculated(void)
 		     temp_idx < ARRAY_SIZE(temperatures); temp_idx++) {
 			cpu_edp_calculated_limits[temp_idx].temperature =
 				temperatures[temp_idx];
-			limit = cpu_edp_calculate_maxf(params,
+			if (temperatures[temp_idx] >= 70 &&
+					tegra_cpu_speedo_id() == 8)
+				limit = 1836000;
+			else
+				limit = cpu_edp_calculate_maxf(params,
 						   temperatures[temp_idx],
 						   -1,
 						   0,
@@ -868,8 +872,8 @@ static int init_gpu_edp_limits_calculated(void)
 			gpu_temperatures[i];
 		if (gpu_temperatures[i] == 0 && tegra_gpu_speedo_id() == 5)
 			limit = 708000;
-		else if (gpu_temperatures[i] == 0 && tegra_gpu_speedo_id() == 6)
-			limit = 852000;
+		else if (gpu_temperatures[i] >= 70 && tegra_gpu_speedo_id() == 6)
+			limit = 804000;
 		else
 			limit = gpu_edp_calculate_maxf(params,
 					       gpu_temperatures[i],
diff --git a/arch/arm/mach-tegra/tegra12_dvfs.c b/arch/arm/mach-tegra/tegra12_dvfs.c
index 145e990dc8f3..e94d86f4b84e 100644
--- a/arch/arm/mach-tegra/tegra12_dvfs.c
+++ b/arch/arm/mach-tegra/tegra12_dvfs.c
@@ -48,14 +48,20 @@ static int gpu_vmin_offsets[] = { 0, -20, };
 static int vdd_core_vmin_trips_table[MAX_THERMAL_LIMITS] = { 20, };
 static int vdd_core_therm_floors_table[MAX_THERMAL_LIMITS] = { 950, };
 
+static int vdd_core_vmin_trips_table_sku80[MAX_THERMAL_LIMITS] = { 0, };
+static int vdd_core_therm_floors_table_sku80[MAX_THERMAL_LIMITS] = { 1100, };
+
+static int vdd_core_vmin_trips_table_sku80_alwayson[MAX_THERMAL_LIMITS] = { 0, };
+static int vdd_core_therm_floors_table_sku80_alwayson[MAX_THERMAL_LIMITS] = { 1000, };
+
 static int vdd_core_vmax_trips_table[MAX_THERMAL_LIMITS] = { 62,   72,   82, };
 static int vdd_core_therm_caps_table[MAX_THERMAL_LIMITS] = { 1130, 1100, 1060, };
 
-static int vdd_core_vmax_trips_table_sku80_alwayson[MAX_THERMAL_LIMITS] = { -40, 0, };
-static int vdd_core_therm_caps_table_sku80_alwayson[MAX_THERMAL_LIMITS] = { 950, 1000, };
+static int vdd_core_vmax_trips_table_sku80_alwayson[] = { -40, 0, };
+static int vdd_core_therm_caps_table_sku80_alwayson[] = { 950, 1000, };
 
-static int vdd_core_vmax_trips_table_sku80[MAX_THERMAL_LIMITS] = { -40, 0, 70};
-static int vdd_core_therm_caps_table_sku80[MAX_THERMAL_LIMITS] = { 1000, 1100, 1050 };
+static int vdd_core_vmax_trips_table_sku80[] = { -40, 0, 70};
+static int vdd_core_therm_caps_table_sku80[] = { 1050, 1100, 1050};
 
 #ifndef CONFIG_TEGRA_CPU_VOLT_CAP
 static int vdd_cpu_vmax_trips_table[MAX_THERMAL_LIMITS] = { 62,   72,   82, };
@@ -159,7 +165,7 @@ void __init tegra12x_vdd_cpu_align(int step_uv, int offset_uv)
 /* CPU DVFS tables */
 static unsigned long cpu_max_freq[] = {
 /* speedo_id	0	 1	  2	   3	    4	     5	      6		7	 8*/
-		2014500, 2320500, 2116500, 2524500, 1811000, 2218500, 1938000, 1912500, 2140000,
+		2014500, 2320500, 2116500, 2524500, 1811000, 2218500, 1912500, 1912500, 2116500,
 };
 
 static struct cpu_cvb_dvfs cpu_cvb_dvfs_table[] = {
@@ -195,9 +201,9 @@ static struct cpu_cvb_dvfs cpu_cvb_dvfs_table[] = {
 		 */
 		.clk_switch_trips = {34,}
 	},
-	/* Entry for Embedded SKU CD575MI Always On*/
+	/* Entry for Embedded SKU CD575M Always On*/
 	{
-		.speedo_id = 7,
+		.speedo_id = 6,
 		.process_id = -1,
 		.dfll_tune_data  = {
 			.tune0		= 0x005020FF,
@@ -207,30 +213,71 @@ static struct cpu_cvb_dvfs cpu_cvb_dvfs_table[] = {
 			.tune_high_min_millivolts = 900,
 			.min_millivolts = 720,
 		},
+		.max_mv = 1120,
+		.freqs_mult = KHZ,
+		.speedo_scale = 100,
+		.voltage_scale = 1000,
+		.cvb_table = {
+			/*f       dfll: c0,     c1,   c2  pll:  c0,   c1,    c2 */
+			{204000,        {1112619, -29295, 402}, {950000, 0, 0}},
+			{306000,	{1150460, -30585, 402}, {950000, 0, 0}},
+			{408000,	{1190122, -31865, 402}, {950000, 0, 0}},
+			{510000,	{1231606, -33155, 402}, {950000, 0, 0}},
+			{612000,	{1274912, -34435, 402}, {950000, 0, 0}},
+			{714000,	{1320040, -35725, 402}, {950000, 0, 0}},
+			{816000,	{1366990, -37005, 402}, {950000, 0, 0}},
+			{918000,	{1415762, -38295, 402}, {950000, 0, 0}},
+			{1020000,	{1466355, -39575, 402}, {950000, 0, 0}},
+			{1122000,	{1518771, -40865, 402}, {950000, 0, 0}},
+			{1224000,	{1573009, -42145, 402}, {970000, 0, 0}},
+			{1326000,	{1629068, -43435, 402}, {1100000, 0, 0}},
+			{1428000,	{1686950, -44715, 402}, {1100000, 0, 0}},
+			{1530000,	{1746653, -46005, 402}, {1100000, 0, 0}},
+			{1632000,	{1808179, -47285, 402}, {1200000, 0, 0}},
+			{1734000,	{1871526, -48575, 402}, {1200000, 0, 0}},
+			{1836000,	{1936696, -49855, 402}, {1200000, 0, 0}},
+			{1912500,	{2003687, -51145, 402}, {1200000, 0, 0}},
+			{      0 , 	{      0,      0,   0}, {}},
+		},
+		.vmin_trips_table = { 20, 35, 55, 75, 120 },
+		.therm_floors_table = { 900, 800, 790, 770, 750, },
+	},
+	/* Entry for Embedded SKU CD575MI Always On*/
+	{
+		.speedo_id = 7,
+		.process_id = -1,
+		.dfll_tune_data  = {
+			.tune0		= 0x005040FF,
+			.tune0_high_mv	= 0x005040FF,
+			.tune1		= 0x00000060,
+			.droop_rate_min = 1000000,
+			.tune_high_min_millivolts = 950,
+			.min_millivolts = 950,
+		},
 		.max_mv = 1100,
 		.freqs_mult = KHZ,
 		.speedo_scale = 100,
 		.voltage_scale = 1000,
 		.cvb_table = {
 			/*f       dfll: c0,     c1,   c2  pll:  c0,   c1,    c2 */
-			{204000,        {1112619, -29295, 402}, {800000, 0, 0}},
-			{306000,	{1150460, -30585, 402}, {800000, 0, 0}},
-			{408000,	{1190122, -31865, 402}, {800000, 0, 0}},
-			{510000,	{1231606, -33155, 402}, {800000, 0, 0}},
-			{612000,	{1274912, -34435, 402}, {800000, 0, 0}},
-			{714000,	{1320040, -35725, 402}, {800000, 0, 0}},
-			{816000,	{1366990, -37005, 402}, {820000, 0, 0}},
-			{918000,	{1415762, -38295, 402}, {840000, 0, 0}},
-			{1020000,	{1466355, -39575, 402}, {880000, 0, 0}},
-			{1122000,	{1518771, -40865, 402}, {900000, 0, 0}},
-			{1224000,	{1573009, -42145, 402}, {930000, 0, 0}},
-			{1326000,	{1629068, -43435, 402}, {960000, 0, 0}},
-			{1428000,	{1686950, -44715, 402}, {990000, 0, 0}},
-			{1530000,	{1746653, -46005, 402}, {1020000, 0, 0}},
-			{1632000,	{1808179, -47285, 402}, {1070000, 0, 0}},
-			{1734000,	{1871526, -48575, 402}, {1100000, 0, 0}},
-			{1836000,	{1936696, -49855, 402}, {1140000, 0, 0}},
-			{1912500,	{2003687, -51145, 402}, {1180000, 0, 0}},
+			{204000,        {1112619, -29295, 402}, {950000, 0, 0}},
+			{306000,	{1150460, -30585, 402}, {950000, 0, 0}},
+			{408000,	{1190122, -31865, 402}, {950000, 0, 0}},
+			{510000,	{1231606, -33155, 402}, {950000, 0, 0}},
+			{612000,	{1274912, -34435, 402}, {950000, 0, 0}},
+			{714000,	{1320040, -35725, 402}, {950000, 0, 0}},
+			{816000,	{1366990, -37005, 402}, {950000, 0, 0}},
+			{918000,	{1415762, -38295, 402}, {950000, 0, 0}},
+			{1020000,	{1466355, -39575, 402}, {950000, 0, 0}},
+			{1122000,	{1518771, -40865, 402}, {950000, 0, 0}},
+			{1224000,	{1573009, -42145, 402}, {970000, 0, 0}},
+			{1326000,	{1629068, -43435, 402}, {1100000, 0, 0}},
+			{1428000,	{1686950, -44715, 402}, {1100000, 0, 0}},
+			{1530000,	{1746653, -46005, 402}, {1100000, 0, 0}},
+			{1632000,	{1808179, -47285, 402}, {1200000, 0, 0}},
+			{1734000,	{1871526, -48575, 402}, {1200000, 0, 0}},
+			{1836000,	{1936696, -49855, 402}, {1200000, 0, 0}},
+			{1912500,	{2003687, -51145, 402}, {1200000, 0, 0}},
 			{      0 , 	{      0,      0,   0}, {}},
 		},
 		/*
@@ -244,12 +291,12 @@ static struct cpu_cvb_dvfs cpu_cvb_dvfs_table[] = {
 		.speedo_id = 8,
 		.process_id = -1,
 		.dfll_tune_data  = {
-			.tune0		= 0x005020FF,
+			.tune0		= 0x005040FF,
 			.tune0_high_mv	= 0x005040FF,
 			.tune1		= 0x00000060,
 			.droop_rate_min = 1000000,
-			.tune_high_min_millivolts = 900,
-			.min_millivolts = 720,
+			.tune_high_min_millivolts = 950,
+			.min_millivolts = 950,
 		},
 		.max_mv = 1210,
 		.freqs_mult = KHZ,
@@ -257,26 +304,26 @@ static struct cpu_cvb_dvfs cpu_cvb_dvfs_table[] = {
 		.voltage_scale = 1000,
 		.cvb_table = {
 			/*f       dfll: c0,     c1,   c2  pll:  c0,   c1,    c2 */
-			{204000,        {1112619, -29295, 402}, {800000, 0, 0}},
-			{306000,	{1150460, -30585, 402}, {800000, 0, 0}},
-			{408000,	{1190122, -31865, 402}, {800000, 0, 0}},
-			{510000,	{1231606, -33155, 402}, {800000, 0, 0}},
-			{612000,	{1274912, -34435, 402}, {800000, 0, 0}},
-			{714000,	{1320040, -35725, 402}, {800000, 0, 0}},
-			{816000,	{1366990, -37005, 402}, {820000, 0, 0}},
-			{918000,	{1415762, -38295, 402}, {840000, 0, 0}},
-			{1020000,	{1466355, -39575, 402}, {880000, 0, 0}},
-			{1122000,	{1518771, -40865, 402}, {900000, 0, 0}},
-			{1224000,	{1573009, -42145, 402}, {930000, 0, 0}},
-			{1326000,	{1629068, -43435, 402}, {960000, 0, 0}},
-			{1428000,	{1686950, -44715, 402}, {990000, 0, 0}},
-			{1530000,	{1746653, -46005, 402}, {1020000, 0, 0}},
-			{1632000,	{1808179, -47285, 402}, {1070000, 0, 0}},
-			{1734000,	{1871526, -48575, 402}, {1100000, 0, 0}},
-			{1836000,	{1936696, -49855, 402}, {1140000, 0, 0}},
-			{1938000,	{2003687, -51145, 402}, {1180000, 0, 0}},
-			{2014500,	{2054787, -52095, 402}, {1220000, 0, 0}},
-			{2116500,	{2124957, -53385, 402}, {1260000, 0, 0}},
+			{204000,        {1112619, -29295, 402}, {950000, 0, 0}},
+			{306000,	{1150460, -30585, 402}, {950000, 0, 0}},
+			{408000,	{1190122, -31865, 402}, {950000, 0, 0}},
+			{510000,	{1231606, -33155, 402}, {950000, 0, 0}},
+			{612000,	{1274912, -34435, 402}, {950000, 0, 0}},
+			{714000,	{1320040, -35725, 402}, {950000, 0, 0}},
+			{816000,	{1366990, -37005, 402}, {950000, 0, 0}},
+			{918000,	{1415762, -38295, 402}, {950000, 0, 0}},
+			{1020000,	{1466355, -39575, 402}, {950000, 0, 0}},
+			{1122000,	{1518771, -40865, 402}, {950000, 0, 0}},
+			{1224000,	{1573009, -42145, 402}, {970000, 0, 0}},
+			{1326000,	{1629068, -43435, 402}, {1100000, 0, 0}},
+			{1428000,	{1686950, -44715, 402}, {1100000, 0, 0}},
+			{1530000,	{1746653, -46005, 402}, {1100000, 0, 0}},
+			{1632000,	{1808179, -47285, 402}, {1130000, 0, 0}},
+			{1734000,	{1871526, -48575, 402}, {1130000, 0, 0}},
+			{1836000,	{1936696, -49855, 402}, {1210000, 0, 0}},
+			{1938000,	{2003687, -51145, 402}, {1300000, 0, 0}},
+			{2014500,	{2054787, -52095, 402}, {1300000, 0, 0}},
+			{2116500,	{2124957, -53385, 402}, {1300000, 0, 0}},
 			{      0 , 	{      0,      0,   0}, {}},
 		},
 		/*
@@ -345,7 +392,7 @@ static struct dvfs cpu_dvfs = {
 };
 
 /* Core DVFS tables */
-static const int core_millivolts[MAX_DVFS_FREQS] = {
+static int core_millivolts[MAX_DVFS_FREQS] = {
 	800, 850, 900, 950, 1000, 1050, 1100, 1110, 1150};
 
 #define CORE_DVFS(_clk_name, _speedo_id, _process_id, _auto, _mult, _freqs...) \
@@ -559,70 +606,70 @@ static struct dvfs core_dvfs_table_embedded[] = {
 	/* Core voltages (mV):		         800,    850,    900,	 950,    1000, 	 1050,	  1100	*/
 	/* Clock limits for internal blocks, PLLs */
 
-	CORE_DVFS("emc",        4, -1, 1, KHZ, 1,      1,      1,      1,	792000,	 792000, 924000),
+	CORE_DVFS("emc",        4, -1, 1, KHZ, 1,      1,      1,      1,	1,	 792000, 924000),
 
-        CORE_DVFS("cpu_lp",     4, -1, 1, KHZ,  1,      1,      1,      1,	1044000, 1044000, 1044000),
+        CORE_DVFS("cpu_lp",     4, -1, 1, KHZ,  1,      1,      1,      1,	1, 1044000, 1044000),
 
-        CORE_DVFS("sbus",       4, -1, 1, KHZ,  1,      1,      1,      1,	348000, 348000, 372000),
+        CORE_DVFS("sbus",       4, -1, 1, KHZ,  1,      1,      1,      1,	1, 348000, 372000),
 
-	CORE_DVFS("vic03",      4, -1, 1, KHZ,  1,      1,      1,      1,	660000, 660000, 708000),
+	CORE_DVFS("vic03",      4, -1, 1, KHZ,  1,      1,      1,      1,	1, 660000, 708000),
 
-	CORE_DVFS("tsec",       4, -1, 1, KHZ,  1,      1,      1,      1,	660000, 660000, 708000),
+	CORE_DVFS("tsec",       4, -1, 1, KHZ,  1,      1,      1,      1,	1, 660000, 708000),
 
-	CORE_DVFS("msenc",      4, -1, 1, KHZ,  1,      1,      1,      1,	432000, 432000, 456000),
+	CORE_DVFS("msenc",      4, -1, 1, KHZ,  1,      1,      1,      1,	1, 432000, 456000),
 
-	CORE_DVFS("se",         4, -1, 1, KHZ,  1,      1,      1,      1,	432000, 432000, 456000),
+	CORE_DVFS("se",         4, -1, 1, KHZ,  1,      1,      1,      1,	1, 432000, 456000),
 
-	CORE_DVFS("vde",        4, -1, 1, KHZ,  1,      1,      1,      1,	432000, 432000, 456000),
+	CORE_DVFS("vde",        4, -1, 1, KHZ,  1,      1,      1,      1,	1, 432000, 456000),
 
-        CORE_DVFS("host1x",     4, -1, 1, KHZ,  1,      1,      1,      1,	372000, 372000, 408000),
+        CORE_DVFS("host1x",     4, -1, 1, KHZ,  1,      1,      1,      1,	1, 372000, 408000),
 
-	CORE_DVFS("vi",         4, -1, 1, KHZ,  1,      1,      1,      1,	600000, 600000, 600000),
+	CORE_DVFS("vi",         4, -1, 1, KHZ,  1,      1,      1,      1,	1, 600000, 600000),
 
-	CORE_DVFS("isp",        4, -1, 1, KHZ,  1,      1,      1,      1,	600000, 600000, 600000),
+	CORE_DVFS("isp",        4, -1, 1, KHZ,  1,      1,      1,      1,	1, 600000, 600000),
 
 #ifdef CONFIG_TEGRA_DUAL_CBUS
-        CORE_DVFS("c2bus",      4, -1, 1, KHZ,  1,      1,      1,      1,	432000, 432000, 456000),
+        CORE_DVFS("c2bus",      4, -1, 1, KHZ,  1,      1,      1,      1,	1, 432000, 456000),
 
-        CORE_DVFS("c3bus",      4, -1, 1, KHZ,  1,      1,      1,      1,	660000, 660000, 708000),
+        CORE_DVFS("c3bus",      4, -1, 1, KHZ,  1,      1,      1,      1,	1, 660000, 708000),
 #else
-	CORE_DVFS("cbus",      4, -1, 1, KHZ,  1,      1,      1,      1,	216000, 216000, 372000),
+	CORE_DVFS("cbus",      4, -1, 1, KHZ,  1,      1,      1,      1,	1, 216000, 372000),
 #endif
 
-	CORE_DVFS("c4bus",      4, -1, 1, KHZ,  1,      1,      1,      1,	600000, 600000, 600000),
+	CORE_DVFS("c4bus",      4, -1, 1, KHZ,  1,      1,      1,      1,	1, 600000, 600000),
 
-	CORE_DVFS("pll_m",  4, -1, 1, KHZ,   1,      1,      1,      1,		1066000, 1066000, 1200000),
-	CORE_DVFS("pll_c",  4, -1, 1, KHZ,   1,      1,      1,      1,		1066000, 1066000, 1066000),
-	CORE_DVFS("pll_c2", 4, -1, 1, KHZ,   1,      1,      1,      1,		1066000, 1066000, 1066000),
-	CORE_DVFS("pll_c3", 4, -1, 1, KHZ,   1,      1,      1,      1,		1066000, 1066000, 1066000),
+	CORE_DVFS("pll_m",  4, -1, 1, KHZ,   1,      1,      1,      1,		1, 1066000, 1200000),
+	CORE_DVFS("pll_c",  4, -1, 1, KHZ,   1,      1,      1,      1,		1, 1066000, 1066000),
+	CORE_DVFS("pll_c2", 4, -1, 1, KHZ,   1,      1,      1,      1,		1, 1066000, 1066000),
+	CORE_DVFS("pll_c3", 4, -1, 1, KHZ,   1,      1,      1,      1,		1, 1066000, 1066000),
 
 	/* Core voltages (mV):		     800,    850,    900,    950,       1000 	1050	1100*/
 	/* Clock limits for I/O peripherals */
-	CORE_DVFS("dsia",   4, -1, 1, KHZ,   1,      1,      1,      1,		750000, 750000, 750000),
-	CORE_DVFS("dsib",   4, -1, 1, KHZ,   1,      1,      1,      1,		750000, 750000, 750000),
-	CORE_DVFS("dsialp", 4, -1, 1, KHZ,   1,      1,      1,      1,		156000, 156000, 156000),
-	CORE_DVFS("dsiblp", 4, -1, 1, KHZ,   1,      1,      1,      1,		156000, 156000, 156000),
-	CORE_DVFS("hdmi",   4, -1, 1, KHZ,   1,      1,      1,      1,		297000, 297000, 297000),
+	CORE_DVFS("dsia",   4, -1, 1, KHZ,   1,      1,      1,      1,		1, 750000, 750000),
+	CORE_DVFS("dsib",   4, -1, 1, KHZ,   1,      1,      1,      1,		1, 750000, 750000),
+	CORE_DVFS("dsialp", 4, -1, 1, KHZ,   1,      1,      1,      1,		1, 156000, 156000),
+	CORE_DVFS("dsiblp", 4, -1, 1, KHZ,   1,      1,      1,      1,		1, 156000, 156000),
+	CORE_DVFS("hdmi",   4, -1, 1, KHZ,   1,      1,      1,      1,		1, 297000, 297000),
 
-	CORE_DVFS("pciex",  4,  -1, 1, KHZ,   1,      1,      1,     1,		500000, 500000, 500000),
-	CORE_DVFS("mselect", 4, -1, 1, KHZ,  1,      1,      1,      1,		204000, 204000, 408000),
+	CORE_DVFS("pciex",  4,  -1, 1, KHZ,   1,      1,      1,     1,		1, 500000, 500000),
+	CORE_DVFS("mselect", 4, -1, 1, KHZ,  1,      1,      1,      1,		1, 204000, 408000),
 
 	/* Core voltages (mV):		         	800,    850,    900,	 950,    1000 	1050	1100*/
 	/* xusb clocks */
-	CORE_DVFS("xusb_falcon_src", 4, -1, 1, KHZ, 	  1,      1,      1,      1,	336000, 336000 ,  336000),
-	CORE_DVFS("xusb_host_src",   4, -1, 1, KHZ,  	  1,      1,      1,      1,	112000, 112000 ,  112000),
-	CORE_DVFS("xusb_dev_src",    4, -1, 1, KHZ,  	  1,      1,      1,      1,	112000, 112000 ,  112000),
-	CORE_DVFS("xusb_ss_src",     4, -1, 1, KHZ,  	  1,      1,      1,      1,	120000, 120000 ,  120000),
-	CORE_DVFS("xusb_fs_src",     4, -1, 1, KHZ,  	  1,      1,      1,      1,	 48000,  48000 ,   48000),
-	CORE_DVFS("xusb_hs_src",     4, -1, 1, KHZ,  	  1,      1,      1,      1,	 60000,  60000 ,   60000),
-
-	CORE_DVFS("hda",    	     4, -1, 1, KHZ,  	  1,      1,      1,      1,	108000, 108000 ,  108000),
-	CORE_DVFS("hda2codec_2x",    4, -1, 1, KHZ,  	  1,      1,      1,      1,	 48000,  48000 ,   48000),
-
-	CORE_DVFS("sor0",            4, -1, 1, KHZ, 	  1,      1,      1,      1,	540000,  540000,  540000),
-	OVRRD_DVFS("sdmmc1",         4, -1, 1, KHZ,      1,      1,  	1,  	1,	136000, 136000, 136000),
-        OVRRD_DVFS("sdmmc3",         4, -1, 1, KHZ,      1,      1,  	1,  	1,	136000, 136000, 136000),
-        OVRRD_DVFS("sdmmc4",         4, -1, 1, KHZ,      1,      1,  	1,  	1,	136000, 136000, 136000),
+	CORE_DVFS("xusb_falcon_src", 4, -1, 1, KHZ, 	  1,      1,      1,      1,	1, 336000 ,  336000),
+	CORE_DVFS("xusb_host_src",   4, -1, 1, KHZ,  	  1,      1,      1,      1,	1, 112000 ,  112000),
+	CORE_DVFS("xusb_dev_src",    4, -1, 1, KHZ,  	  1,      1,      1,      1,	1, 112000 ,  112000),
+	CORE_DVFS("xusb_ss_src",     4, -1, 1, KHZ,  	  1,      1,      1,      1,	1, 120000 ,  120000),
+	CORE_DVFS("xusb_fs_src",     4, -1, 1, KHZ,  	  1,      1,      1,      1,	 1,  48000 ,   48000),
+	CORE_DVFS("xusb_hs_src",     4, -1, 1, KHZ,  	  1,      1,      1,      1,	 1,  60000 ,   60000),
+
+	CORE_DVFS("hda",    	     4, -1, 1, KHZ,  	  1,      1,      1,      1,	1, 108000 ,  108000),
+	CORE_DVFS("hda2codec_2x",    4, -1, 1, KHZ,  	  1,      1,      1,      1,	 1,  48000 ,   48000),
+
+	CORE_DVFS("sor0",            4, -1, 1, KHZ, 	  1,      1,      1,      1,	1,  540000,  540000),
+	OVRRD_DVFS("sdmmc1",         4, -1, 1, KHZ,      1,      1,  	1,  	1,	1, 136000, 136000),
+        OVRRD_DVFS("sdmmc3",         4, -1, 1, KHZ,      1,      1,  	1,  	1,	1, 136000, 136000),
+        OVRRD_DVFS("sdmmc4",         4, -1, 1, KHZ,      1,      1,  	1,  	1,	1, 136000, 136000),
 };
 
 static struct dvfs core_dvfs_table_automotive[] = {
@@ -717,7 +764,7 @@ static int resolve_core_override(int min_override_mv)
 /* GPU DVFS tables */
 static unsigned long gpu_max_freq[] = {
 /* speedo_id	0	1	2	 3	 4	 5	 6*/
-		648000, 852000, 1008000, 600000, 804000, 756000, 924000
+		648000, 852000, 1008000, 600000, 804000, 756000, 852000
 };
 static struct gpu_cvb_dvfs gpu_cvb_dvfs_table[] = {
 	{
@@ -738,10 +785,42 @@ static struct gpu_cvb_dvfs gpu_cvb_dvfs_table[] = {
 		.vts_trips_table = { -40, 35, },
 	},
 	{
+		/* Embedded SKU CD575M Always On*/
+		.speedo_id =  4,
+		.process_id = -1,
+		.max_mv = 1090,
+		.freqs_mult = KHZ,
+		.speedo_scale = 100,
+		.thermal_scale = 10,
+		.voltage_scale = 1000,
+		.cvb_table = {
+			/*f        dfll  pll:   c0,     c1,   c2,   c3,      c4,   c5 */
+			{   72000, {  }, { 1209886, -36468,  515,   417, -13123,  203}, },
+			{  108000, {  }, { 1130804, -27659,  296,   298, -10834,  221}, },
+			{  180000, {  }, { 1162871, -27110,  247,   238, -10681,  268}, },
+			{  252000, {  }, { 1220458, -28654,  247,   179, -10376,  298}, },
+			{  324000, {  }, { 1280953, -30204,  247,   119,  -9766,  304}, },
+			{  396000, {  }, { 1344547, -31777,  247,   119,  -8545,  292}, },
+			{  468000, {  }, { 1420168, -34227,  269,    60,  -7172,  256}, },
+			{  540000, {  }, { 1490757, -35955,  274,    60,  -5188,  197}, },
+			{  612000, {  }, { 1599112, -42583,  398,     0,  -1831,  119}, },
+			{  648000, {  }, { 1366986, -16459, -274,     0,  -3204,   72}, },
+			{  684000, {  }, { 1391884, -17078, -274,   -60,  -1526,   30}, },
+			{  708000, {  }, { 1415522, -17497, -274,   -60,   -458,    0}, },
+			{  756000, {  }, { 1464061, -18331, -274,  -119,   1831,  -72}, },
+			{  804000, {  }, { 1524225, -20064, -254,  -119,   4272, -155}, },
+			{       0, {  }, { }, },
+		},
+		.cvb_vmin =  {  0, {  }, { 1180000, -18900,    0,     0,  -6110,    0}, },
+		.vmin_trips_table = { 15, },
+		.therm_floors_table = { 900, },
+		.vts_trips_table = { -10, 10, 30, 50, 70, },
+	},
+	{
 		/* Embedded SKU CD575MI Always On*/
 		.speedo_id =  5,
 		.process_id = -1,
-		.max_mv = 1090,
+		.max_mv = 1070,
 		.freqs_mult = KHZ,
 		.speedo_scale = 100,
 		.thermal_scale = 10,
@@ -760,7 +839,7 @@ static struct gpu_cvb_dvfs gpu_cvb_dvfs_table[] = {
 			{  648000, {  }, { 1366986, -16459, -274,  }, },
 			{  684000, {  }, { 1391884, -17078, -274,  }, },
 			{  708000, {  }, { 1415522, -17497, -274,  }, },
-			{  756000, {  }, { 1464061, -18331, -274,  }, },
+			{  756000, {  }, { 1494061, -18331, -274,  }, },
 			{       0, {  }, { }, },
 		},
 		.cvb_vmin =  { 0, { } , { 950000, }, },
@@ -789,11 +868,9 @@ static struct gpu_cvb_dvfs gpu_cvb_dvfs_table[] = {
 			{  648000, {  }, { 1366986, -16459, -274,  }, },
 			{  684000, {  }, { 1391884, -17078, -274,  }, },
 			{  708000, {  }, { 1415522, -17497, -274,  }, },
-			{  756000, {  }, { 1464061, -18331, -274,  }, },
+			{  756000, {  }, { 1494061, -18331, -274,  }, },
 			{  804000, {  }, { 1524225, -20064, -254,  }, },
                         {  852000, {  }, { 1608418, -21643, -269,  }, },
-			{  900000, {  }, { 1706383, -25155, -209,  }, },
-			{  924000, {  }, { 1739600, -26289, -194,  }, },
 			{       0, {  }, { }, },
 		},
 		.cvb_vmin =  { 0, { } , { 950000, }, },
@@ -1286,8 +1363,10 @@ static int __init set_gpu_dvfs_data(unsigned long max_freq,
 			/* clip to minimum, abort if above maximum */
 			mvj_offs = max(mvj, gpu_vmin[j] + simon_offs);
 			mvj = max(mvj, gpu_vmin[j]);
-			if (mvj > d->max_mv)
-				break;
+			if ((d->speedo_id != 5) || (j != 0)) {
+				if (mvj > d->max_mv)
+					break;
+			}
 
 			/* update voltage for adjacent ranges bounded by this
 			   trip-point (cvb & dvfs are transpose matrices) */
@@ -1440,6 +1519,7 @@ void __init tegra12x_init_dvfs(void)
 	int core_process_id = tegra_core_process_id();
 	int gpu_speedo_id = tegra_gpu_speedo_id();
 	int gpu_process_id = tegra_gpu_process_id();
+	int chip_personality = tegra_get_chip_personality();
 
 	int i, ret;
 	int core_nominal_mv_index;
@@ -1466,8 +1546,17 @@ void __init tegra12x_init_dvfs(void)
 	if (cpu_speedo_id == 7 || cpu_speedo_id == 8 ||
 		CONFIG_TEGRA_USE_DFLL_RANGE == TEGRA_USE_DFLL_CDEV_CNTRL)
 		tegra_override_dfll_range = TEGRA_USE_DFLL_CDEV_CNTRL;
-	if (soc_speedo_id == 3 || soc_speedo_id == 4)
+	if (soc_speedo_id == 3)
 		tegra_dvfs_core_disabled = true;
+	/* update core dvfs nominal voltage for CD575M always on profile */
+	if (soc_speedo_id == 0 && chip_personality == always_on) {
+		for (i = 0; i < MAX_DVFS_FREQS; i++) {
+			if (core_millivolts[i] == 1000) {
+				core_millivolts[i] = 1010;
+				break;
+			}
+		}
+	}
 	/*
 	 * Find nominal voltages for core (1st) and cpu rails before rail
 	 * init. Nominal voltage index in core scaling ladder can also be
@@ -1528,9 +1617,9 @@ void __init tegra12x_init_dvfs(void)
 	BUG_ON((i == ARRAY_SIZE(gpu_cvb_dvfs_table)) || ret);
 
 	/* Init core thermal profile */
-	tegra_dvfs_rail_init_vmin_thermal_profile(vdd_core_vmin_trips_table,
-		vdd_core_therm_floors_table, &tegra12_dvfs_rail_vdd_core, NULL);
 	if (soc_speedo_id == 3) {
+		tegra_dvfs_rail_init_vmin_thermal_profile(vdd_core_vmin_trips_table_sku80_alwayson,
+				vdd_core_therm_floors_table_sku80_alwayson, &tegra12_dvfs_rail_vdd_core, NULL);
 		tegra12_dvfs_rail_vdd_core.therm_mv_caps = vdd_core_therm_caps_table_sku80_alwayson;
 		tegra12_dvfs_rail_vdd_core.therm_mv_caps_num = ARRAY_SIZE(vdd_core_therm_caps_table_sku80_alwayson);
 		if (tegra12_dvfs_rail_vdd_core.vmax_cdev) {
@@ -1539,6 +1628,8 @@ void __init tegra12x_init_dvfs(void)
 			tegra12_dvfs_rail_vdd_core.vmax_cdev->trip_temperatures = vdd_core_vmax_trips_table_sku80_alwayson;
 		}
 	} else if (soc_speedo_id == 4) {
+		tegra_dvfs_rail_init_vmin_thermal_profile(vdd_core_vmin_trips_table_sku80,
+				vdd_core_therm_floors_table_sku80, &tegra12_dvfs_rail_vdd_core, NULL);
 		tegra12_dvfs_rail_vdd_core.therm_mv_caps = vdd_core_therm_caps_table_sku80;
 		tegra12_dvfs_rail_vdd_core.therm_mv_caps_num = ARRAY_SIZE(vdd_core_therm_caps_table_sku80);
 		if (tegra12_dvfs_rail_vdd_core.vmax_cdev) {
@@ -1546,9 +1637,12 @@ void __init tegra12x_init_dvfs(void)
 				ARRAY_SIZE(vdd_core_vmax_trips_table_sku80);
 			tegra12_dvfs_rail_vdd_core.vmax_cdev->trip_temperatures = vdd_core_vmax_trips_table_sku80;
 		}
-	} else
+	} else {
+		tegra_dvfs_rail_init_vmin_thermal_profile(vdd_core_vmin_trips_table,
+				vdd_core_therm_floors_table, &tegra12_dvfs_rail_vdd_core, NULL);
 		tegra_dvfs_rail_init_vmax_thermal_profile(vdd_core_vmax_trips_table,
-			vdd_core_therm_caps_table, &tegra12_dvfs_rail_vdd_core, NULL);
+				vdd_core_therm_caps_table, &tegra12_dvfs_rail_vdd_core, NULL);
+	}
 
 	/* Init rail structures and dependencies */
 	tegra_dvfs_init_rails(tegra12_dvfs_rails,
diff --git a/arch/arm/mach-tegra/tegra_core_volt_cap.c b/arch/arm/mach-tegra/tegra_core_volt_cap.c
index 2b03faf811f4..abf805f97d30 100644
--- a/arch/arm/mach-tegra/tegra_core_volt_cap.c
+++ b/arch/arm/mach-tegra/tegra_core_volt_cap.c
@@ -271,7 +271,7 @@ static int __init init_core_cap_one(struct clk *c, unsigned long *freqs)
 			if (rate == next_rate)
 				break;
 
-			next_v = tegra_dvfs_predict_peak_millivolts(
+			next_v = tegra_dvfs_predict_millivolts(
 				c->parent, next_rate);
 			if (IS_ERR_VALUE(next_v)) {
 				pr_debug("%s: failed to predict %s mV for rate %lu\n",