diff options
| author | Deepesh Gujarathi <dgujarathi@nvidia.com> | 2010-04-01 18:42:19 +0530 |
|---|---|---|
| committer | Gary King <gking@nvidia.com> | 2010-04-01 16:48:00 -0800 |
| commit | 0f29062f22c119d305eec613bfae1b2c8a6983f4 (patch) | |
| tree | ad545e67044f841fbca237501ec57e96cbb51e0d /arch | |
| parent | 4b115fddc0a3358f6f7ef5c85ad13c45ea5ba27c (diff) | |
tegra pcie: add the VDD_1V5 power rail to the pcie guid
As per the harmony power tree VDDIO_PEX_CLK is the T20's
3.3V PCIe supply. It is sourced from LDO0 of the PMU. By
default, LDO0 is off.
VDD_1V5 is the 1.5V supply for the PCI Express Mini Card
connectors. It turns on automatically in tandem with the
general-purpose 3.3V domain.
If there are no active pcie devices on the bus turn off
the VDD_1V5 power rail.
Change-Id: I518368937aa36e7c73fbb93c28a39706903a614d
Reviewed-on: http://git-master/r/1019
Reviewed-by: Kenneth A Radtke <kradtke@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
Diffstat (limited to 'arch')
| -rwxr-xr-x[-rw-r--r--] | arch/arm/mach-tegra/odm_kit/query/harmony/subboards/nvodm_query_discovery_e1162_addresses.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/odm_kit/query/harmony/subboards/nvodm_query_discovery_e1162_addresses.h b/arch/arm/mach-tegra/odm_kit/query/harmony/subboards/nvodm_query_discovery_e1162_addresses.h index 5462018b2f54..337dc84ff048 100644..100755 --- a/arch/arm/mach-tegra/odm_kit/query/harmony/subboards/nvodm_query_discovery_e1162_addresses.h +++ b/arch/arm/mach-tegra/odm_kit/query/harmony/subboards/nvodm_query_discovery_e1162_addresses.h @@ -235,7 +235,8 @@ static const NvOdmIoAddress s_VddSocAddresses[]= static const NvOdmIoAddress s_VddPexClkAddresses[] = { { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO0 }, /* VDDIO_PEX_CLK -> LDO0 */ - { NvOdmIoModule_Vdd, 0x00, Ext_TPS62290PmuSupply_BUCK } /* AVDD_PLLE -> VDD_1V05 */ + { NvOdmIoModule_Vdd, 0x00, Ext_TPS62290PmuSupply_BUCK }, /* AVDD_PLLE -> VDD_1V05 */ + { NvOdmIoModule_Vdd, 0x00, Ext_TPS74201PmuSupply_LDO }, /* PMU_GPIO-1 -> VDD_1V5 */ }; // PMU0 |