diff options
| author | Alex Frid <afrid@nvidia.com> | 2010-03-25 22:18:55 -0700 |
|---|---|---|
| committer | Gary King <gking@nvidia.com> | 2010-03-29 17:20:29 -0800 |
| commit | a1f7a9e6296396975eadbca615fe7788e2a0c350 (patch) | |
| tree | 8f218a253cee1616f1ed86740082e6445425253e /arch | |
| parent | a3644ba3a01c41f789432bbb75c9dbba004d3664 (diff) | |
tegra RM: Updated graphics clock control.
Updated graphics clock control: added 2D/EPP frequency scaling following
EMC clock, and reduced Host1x clock to 108 MHz to make sure it can be
run at low voltage always (per previous evaluation Host1x at 83MHz works
well with 240MHz cap on modules behind Host, hence 108MHz setting with
current 300 MHz module cap).
Change-Id: I9d5d89b38f08b99a805ad22459a84cb580dce05c
Reviewed-on: http://git-master/r/981
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-tegra/nvrm/core/ap15/nvrm_clocks.c | 1 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_clock_config.c | 9 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_clocks.h | 3 |
3 files changed, 10 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/nvrm_clocks.c b/arch/arm/mach-tegra/nvrm/core/ap15/nvrm_clocks.c index 602f67bc5520..40e8837f9e11 100644 --- a/arch/arm/mach-tegra/nvrm/core/ap15/nvrm_clocks.c +++ b/arch/arm/mach-tegra/nvrm/core/ap15/nvrm_clocks.c @@ -2758,6 +2758,7 @@ static const NvRmModuleID s_Ap20PllC0UsagePolicy[] = NvRmModuleID_Tvo, NvRmModuleID_3D, NvRmModuleID_2D, + NvRmModuleID_Epp, NvRmModuleID_Mpe, NvRmModuleID_Hdmi, NvRmModuleID_Vde diff --git a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_clock_config.c b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_clock_config.c index 76943e28624c..46d6f4edd004 100644 --- a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_clock_config.c +++ b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_clock_config.c @@ -774,13 +774,16 @@ NvRmPrivAp20GetEmcSyncFreq( { case NvRmModuleID_2D: case NvRmModuleID_Epp: - // TODO: establish scales after Ap20 bring-up + // Scale down 2D/EPP whith EMC clock (set 2D/EPP frequency at + // 50% of max when EMC clock is at or below 50% of max) FreqKHz = NvRmPrivGetSocClockLimits(Module)->MaxKHz; + if ((0 < s_Ap20EmcConfig.Index) && + (s_Ap20EmcConfig.Index < NVRM_AP20_DFS_EMC_FREQ_STEPS)) + FreqKHz >>= 1; break; case NvRmModuleID_GraphicsHost: - // TODO: establish level after Ap20 bring-up - FreqKHz = NvRmPrivGetSocClockLimits(Module)->MaxKHz; + FreqKHz = NVRM_AP20_HOST_KHZ; break; default: diff --git a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_clocks.h b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_clocks.h index 0179bccdb90b..04d9bf0734b1 100644 --- a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_clocks.h +++ b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_clocks.h @@ -57,6 +57,9 @@ extern const NvU32 g_Ap20ModuleClockTableSize; // Defines maximum APB frequency (bug 559823) #define NVRM_AP20_APB_MAX_KHZ (125000) +// Defines graphics Host frequency +#define NVRM_AP20_HOST_KHZ (108000) + /** * Defines frequency steps derived from PLLP0 fixed output to be used as System * clock source frequency. The frequency specified in kHz, and it will be rounded |