Fixing emc_log for AP20

patch: removing extra spaces

Change-Id: Icc7fa7d5744134c0846b99c77b90cd76f9f938fc
Reviewed-on: http://git-master/r/1068
Tested-by: Sharad Ranjan <shranjan@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>

3 files changed, 193 insertions, 3 deletions

diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_memctrl.c b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_memctrl.c
index 944950428d00..e5da471f42a8 100644..100755
--- a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_memctrl.c
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_memctrl.c
@@ -79,8 +79,8 @@ static const NvU32 ObsInfoTableSize =
     NV_ARRAY_SIZE(ObsInfoTable);
 
 
-void
-McStat_Start(
+static void
+McStatAp1x_Start(
         NvRmDeviceHandle rm,
         NvU32 client_id_0,
         NvU32 client_id_1,
@@ -176,7 +176,29 @@ McStat_Start(
 }
 
 void
-McStat_Stop(
+McStat_Start(
+        NvRmDeviceHandle rm,
+        NvU32 client_id_0,
+        NvU32 client_id_1,
+        NvU32 llc_client_id)
+{
+    switch (rm->ChipId.Id)
+    {
+        case 0x15:
+        case 0x16:
+            McStatAp1x_Start(rm, client_id_0, client_id_1, llc_client_id);
+            break;
+        case 0x20:
+            McStatAp20_Start(rm, client_id_0, client_id_1, llc_client_id);
+            break;
+        default:
+            NV_ASSERT(!"Unsupported chip ID");
+            break;
+    }
+}
+
+static void
+McStatAp1x_Stop(
         NvRmDeviceHandle rm,
         NvU32 *client_0_cycles,
         NvU32 *client_1_cycles,
@@ -197,6 +219,31 @@ McStat_Stop(
 }
 
 void
+McStat_Stop(
+        NvRmDeviceHandle rm,
+        NvU32 *client_0_cycles,
+        NvU32 *client_1_cycles,
+        NvU32 *llc_client_cycles,
+        NvU32 *llc_client_clocks,
+        NvU32 *mc_clocks)
+{
+    switch (rm->ChipId.Id)
+    {
+        case 0x15:
+        case 0x16:
+            McStatAp1x_Stop(rm, client_0_cycles, client_1_cycles, llc_client_cycles, llc_client_clocks, mc_clocks );
+            break;
+        case 0x20:
+            McStatAp20_Stop(rm, client_0_cycles, client_1_cycles, llc_client_cycles, llc_client_clocks, mc_clocks );
+            break;
+        default:
+            NV_ASSERT(!"Unsupported chip ID");
+            break;
+    }
+}
+
+
+void
 McStat_Report(
         NvU32 client_id_0,
         NvU32 client_0_cycles,
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_private.h b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_private.h
index 6d8a99037952..ed39fe1826b5 100644..100755
--- a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_private.h
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_private.h
@@ -299,6 +299,15 @@ void NvRmPrivAp15SetupMc(NvRmDeviceHandle hRm);
 /** This API sets up the memory controller for AP20. */
 void NvRmPrivAp20SetupMc(NvRmDeviceHandle hRm);
 
+/** This API sets up AP20 MC for stat collection */
+void McStatAp20_Start(NvRmDeviceHandle rm, NvU32 client_id_0, NvU32 client_id_1, NvU32 llc_client_id);
+
+/** This API stops stat collection  for AP20 MC */
+void McStatAp20_Stop(NvRmDeviceHandle rm, NvU32 *client_0_cycles,
+                      NvU32 *client_1_cycles, NvU32 *llc_client_cycles,
+                      NvU32 *llc_client_clocks, NvU32 *mc_clocks);
+
+
 /* init and deinit the keylist */
 NvError NvRmPrivInitKeyList(NvRmDeviceHandle hRm, const NvU32*, NvU32);
 void NvRmPrivDeInitKeyList(NvRmDeviceHandle hRm);
diff --git a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_memctrl.c b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_memctrl.c
index 373422c888df..a1433660c50a 100644..100755
--- a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_memctrl.c
+++ b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_memctrl.c
@@ -35,6 +35,7 @@
 #include "nvos.h"
 #include "nvrm_module.h"
 #include "ap20/armc.h"
+#include "ap20/aremc.h"
 #include "ap20/arahb_arbc.h"
 #include "nvrm_drf.h"
 #include "nvrm_hwintf.h"
@@ -46,6 +47,21 @@ void NvRmPrivAp20SetupMc(NvRmDeviceHandle hRm);
 static void McErrorIntHandler(void* args);
 static NvOsInterruptHandle s_McInterruptHandle = NULL;
 
+void
+McStatAp20_Start(
+        NvRmDeviceHandle rm,
+        NvU32 client_id_0,
+        NvU32 client_id_1,
+        NvU32 llc_client_id);
+void
+McStatAp20_Stop(
+        NvRmDeviceHandle rm,
+        NvU32 *client_0_cycles,
+        NvU32 *client_1_cycles,
+        NvU32 *llc_client_cycles,
+        NvU32 *llc_client_clocks,
+        NvU32 *mc_clocks);
+
 void McErrorIntHandler(void* args)
 {
     NvU32 RegVal;
@@ -162,3 +178,121 @@ void NvRmPrivAp20SetupMc(NvRmDeviceHandle hRm)
 }
 
 
+
+void
+McStatAp20_Start(
+        NvRmDeviceHandle rm,
+        NvU32 client_id_0,
+        NvU32 client_id_1,
+        NvU32 llc_client_id)
+{
+    NvU32 emc_ctrl =
+      (AREMC_STAT_CONTROL_MODE_BANDWIDTH << AREMC_STAT_CONTROL_MODE_SHIFT) |
+      (AREMC_STAT_CONTROL_EVENT_QUALIFIED << AREMC_STAT_CONTROL_EVENT_SHIFT) |
+      (AREMC_STAT_CONTROL_CLIENT_TYPE_MPCORER <<
+         AREMC_STAT_CONTROL_CLIENT_TYPE_SHIFT) |  // default is MPCORE Read client
+      (AREMC_STAT_CONTROL_FILTER_CLIENT_ENABLE <<
+         AREMC_STAT_CONTROL_FILTER_CLIENT_SHIFT) |
+      (AREMC_STAT_CONTROL_FILTER_ADDR_DISABLE <<
+         AREMC_STAT_CONTROL_FILTER_ADDR_SHIFT);
+
+    NvU32 mc_filter_client_0 = (ARMC_STAT_CONTROL_FILTER_CLIENT_ENABLE <<
+                   ARMC_STAT_CONTROL_FILTER_CLIENT_SHIFT);
+
+    NvU32 mc_filter_client_1 = (ARMC_STAT_CONTROL_FILTER_CLIENT_ENABLE <<
+                   ARMC_STAT_CONTROL_FILTER_CLIENT_SHIFT);
+
+    if (client_id_0 == 0xffffffff)
+    {
+        mc_filter_client_0 = (ARMC_STAT_CONTROL_FILTER_CLIENT_DISABLE <<
+                   ARMC_STAT_CONTROL_FILTER_CLIENT_SHIFT);
+        client_id_0 = 0;
+    }
+
+    if (client_id_1 == 0xffffffff)
+    {
+        mc_filter_client_1 = (ARMC_STAT_CONTROL_FILTER_CLIENT_DISABLE <<
+                   ARMC_STAT_CONTROL_FILTER_CLIENT_SHIFT);
+        client_id_1 = 0;
+    }
+
+    if(llc_client_id == 1)
+        emc_ctrl |= AREMC_STAT_CONTROL_CLIENT_TYPE_MPCORER <<
+                    AREMC_STAT_CONTROL_CLIENT_TYPE_SHIFT;
+                    // overwrite with MPCore read
+        NV_REGW(rm, NvRmPrivModuleID_ExternalMemoryController,
+                0, EMC_STAT_CONTROL_0,
+                NV_DRF_DEF(EMC, STAT_CONTROL, LLMC_GATHER,DISABLE));
+        NV_REGW(rm, NvRmPrivModuleID_ExternalMemoryController,
+                0, EMC_STAT_LLMC_CLOCK_LIMIT_0, 0xffffffff);
+        NV_REGW(rm, NvRmPrivModuleID_ExternalMemoryController,
+                0, EMC_STAT_LLMC_CONTROL_0_0, emc_ctrl);
+        NV_REGW(rm, NvRmPrivModuleID_ExternalMemoryController,
+                0, EMC_STAT_CONTROL_0,
+                NV_DRF_DEF(EMC, STAT_CONTROL, LLMC_GATHER, CLEAR));
+        NV_REGW(rm, NvRmPrivModuleID_ExternalMemoryController,
+                0, EMC_STAT_CONTROL_0,
+                NV_DRF_DEF(EMC, STAT_CONTROL, LLMC_GATHER, ENABLE));
+        NV_REGW(rm, NvRmPrivModuleID_MemoryController,
+                0, MC_STAT_CONTROL_0,
+                NV_DRF_DEF(MC, STAT_CONTROL, EMC_GATHER, DISABLE));
+        NV_REGW(rm, NvRmPrivModuleID_MemoryController,
+                0, MC_STAT_EMC_CLOCK_LIMIT_0, 0xffffffff);
+        NV_REGW(rm, NvRmPrivModuleID_MemoryController,
+                0, MC_STAT_EMC_CONTROL_0_0,
+                (ARMC_STAT_CONTROL_MODE_BANDWIDTH <<
+                   ARMC_STAT_CONTROL_MODE_SHIFT) |
+                (client_id_0 << ARMC_STAT_CONTROL_CLIENT_ID_SHIFT) |
+                (ARMC_STAT_CONTROL_EVENT_QUALIFIED <<
+                   ARMC_STAT_CONTROL_EVENT_SHIFT) |
+                mc_filter_client_0 |
+                (ARMC_STAT_CONTROL_FILTER_ADDR_DISABLE <<
+                   ARMC_STAT_CONTROL_FILTER_ADDR_SHIFT) |
+                (ARMC_STAT_CONTROL_FILTER_PRI_DISABLE <<
+                   ARMC_STAT_CONTROL_FILTER_PRI_SHIFT) |
+                (ARMC_STAT_CONTROL_FILTER_COALESCED_DISABLE <<
+                   ARMC_STAT_CONTROL_FILTER_COALESCED_SHIFT));
+        NV_REGW(rm, NvRmPrivModuleID_MemoryController,
+                0, MC_STAT_EMC_CONTROL_1_0,
+                (ARMC_STAT_CONTROL_MODE_BANDWIDTH <<
+                   ARMC_STAT_CONTROL_MODE_SHIFT) |
+                (client_id_1 << ARMC_STAT_CONTROL_CLIENT_ID_SHIFT) |
+                (ARMC_STAT_CONTROL_EVENT_QUALIFIED <<
+                   ARMC_STAT_CONTROL_EVENT_SHIFT) |
+                mc_filter_client_1 |
+                (ARMC_STAT_CONTROL_FILTER_ADDR_DISABLE <<
+                   ARMC_STAT_CONTROL_FILTER_ADDR_SHIFT) |
+                (ARMC_STAT_CONTROL_FILTER_PRI_DISABLE <<
+                   ARMC_STAT_CONTROL_FILTER_PRI_SHIFT) |
+                (ARMC_STAT_CONTROL_FILTER_COALESCED_DISABLE <<
+                   ARMC_STAT_CONTROL_FILTER_COALESCED_SHIFT));
+
+        NV_REGW(rm, NvRmPrivModuleID_MemoryController,
+                0, MC_STAT_CONTROL_0,
+                NV_DRF_DEF(MC, STAT_CONTROL, EMC_GATHER, CLEAR));
+        NV_REGW(rm, NvRmPrivModuleID_MemoryController,
+                0, MC_STAT_CONTROL_0,
+                NV_DRF_DEF(MC, STAT_CONTROL, EMC_GATHER, ENABLE));
+}
+
+
+void
+McStatAp20_Stop(
+        NvRmDeviceHandle rm,
+        NvU32 *client_0_cycles,
+        NvU32 *client_1_cycles,
+        NvU32 *llc_client_cycles,
+        NvU32 *llc_client_clocks,
+        NvU32 *mc_clocks)
+{
+    *llc_client_cycles = NV_REGR(rm, NvRmPrivModuleID_ExternalMemoryController,
+                           0, EMC_STAT_LLMC_COUNT_0_0);
+    *llc_client_clocks = NV_REGR(rm, NvRmPrivModuleID_ExternalMemoryController,
+                           0, EMC_STAT_LLMC_CLOCKS_0);
+    *client_0_cycles = NV_REGR(rm, NvRmPrivModuleID_MemoryController,
+                         0, MC_STAT_EMC_COUNT_0_0);
+    *client_1_cycles = NV_REGR(rm, NvRmPrivModuleID_MemoryController,
+                         0, MC_STAT_EMC_COUNT_1_0);
+    *mc_clocks = NV_REGR(rm, NvRmPrivModuleID_MemoryController,
+                   0, MC_STAT_EMC_CLOCKS_0);
+}