ENGR00235370-3 mx6: hdmidongle: Add new board HDMI dongle.

Add machine layer file for HDMI dongle
Modify kconfig and makefile for HDMI dongle
Add new machine type in arch/arm/tools/mach-types

Signed-off-by: Zhang Xiaodong <B39117@freescale.com>

9 files changed, 1546 insertions, 4 deletions

diff --git a/arch/arm/configs/imx6_android_defconfig b/arch/arm/configs/imx6_android_defconfig
index 0d0e0a3ac67a..febbb79344f2 100644
--- a/arch/arm/configs/imx6_android_defconfig
+++ b/arch/arm/configs/imx6_android_defconfig
@@ -134,6 +134,7 @@ CONFIG_PERF_EVENTS=y
 # CONFIG_PERF_COUNTERS is not set
 # CONFIG_DEBUG_PERF_USE_VMALLOC is not set
 CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_PCI_QUIRKS=y
 CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
@@ -332,11 +333,12 @@ CONFIG_MACH_MX6Q_ARM2=y
 CONFIG_MACH_MX6Q_SABRELITE=y
 CONFIG_MACH_MX6Q_SABRESD=y
 CONFIG_MACH_MX6Q_SABREAUTO=y
+CONFIG_MACH_MX6Q_HDMIDONGLE=y
 
 #
 # MX6 Options:
 #
-# CONFIG_IMX_PCIE is not set
+CONFIG_IMX_PCIE=y
 CONFIG_USB_EHCI_ARC_H1=y
 CONFIG_USB_FSL_ARC_OTG=y
 # CONFIG_MX6_INTER_LDO_BYPASS is not set
@@ -409,8 +411,18 @@ CONFIG_ARM_GIC=y
 # Bus support
 #
 CONFIG_ARM_AMBA=y
-# CONFIG_PCI_SYSCALL is not set
+CONFIG_PCI=y
+CONFIG_PCI_SYSCALL=y
 # CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIEAER=y
+# CONFIG_PCIE_ECRC is not set
+# CONFIG_PCIEAER_INJECT is not set
+CONFIG_PCIEASPM=y
+# CONFIG_PCIEASPM_DEBUG is not set
 # CONFIG_PCCARD is not set
 # CONFIG_ARM_ERRATA_764369 is not set
 # CONFIG_PL310_ERRATA_769419 is not set
@@ -1077,7 +1089,7 @@ CONFIG_MTD_NAND=y
 # CONFIG_MTD_NAND_GPIO is not set
 # CONFIG_MTD_NAND_DISKONCHIP is not set
 # CONFIG_MTD_NAND_NANDSIM is not set
-# CONFIG_MTD_NAND_GPMI_NAND is not set
+CONFIG_MTD_NAND_GPMI_NAND=y
 # CONFIG_MTD_NAND_PLATFORM is not set
 # CONFIG_MTD_ALAUDA is not set
 # CONFIG_MTD_ONENAND is not set
@@ -1269,12 +1281,14 @@ CONFIG_WLAN=y
 # CONFIG_WIFI_CONTROL_FUNC is not set
 # CONFIG_ATH_COMMON is not set
 # CONFIG_BCM4329 is not set
+CONFIG_BCM4330=m
 # CONFIG_BCMDHD is not set
 CONFIG_HOSTAP=y
 # CONFIG_HOSTAP_FIRMWARE is not set
 # CONFIG_IWM is not set
 # CONFIG_LIBERTAS is not set
 # CONFIG_MWIFIEX is not set
+CONFIG_RTL8192CE=m
 
 #
 # Enable WiMAX (Networking options) to see the WiMAX drivers
@@ -1761,7 +1775,8 @@ CONFIG_MFD_CORE=y
 # CONFIG_MFD_MAX8997 is not set
 # CONFIG_MFD_MAX8998 is not set
 # CONFIG_MFD_WM8400 is not set
-# CONFIG_MFD_WM831X_I2C is not set
+CONFIG_MFD_WM831X=y
+CONFIG_MFD_WM831X_I2C=y
 # CONFIG_MFD_WM831X_SPI is not set
 # CONFIG_MFD_WM8350_I2C is not set
 CONFIG_MFD_WM8994=y
diff --git a/arch/arm/mach-mx6/Kconfig b/arch/arm/mach-mx6/Kconfig
index 2ffd90d06a06..e7a3580094e3 100644
--- a/arch/arm/mach-mx6/Kconfig
+++ b/arch/arm/mach-mx6/Kconfig
@@ -251,6 +251,36 @@ config MACH_MX6Q_SABREAUTO
 	  Include support for i.MX 6Quad SABRE Auto platform. This includes specific
 	  configurations for the board and its peripherals.
 
+config MACH_MX6Q_HDMIDONGLE
+	bool "Support i.MX 6Quad HDMIDONGLE platform"
+	select ARCH_MX6Q
+	select SOC_IMX6Q
+	select IMX_HAVE_PLATFORM_IMX_UART
+	select IMX_HAVE_PLATFORM_DMA
+	select IMX_HAVE_PLATFORM_GPMI_NFC
+	select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+	select IMX_HAVE_PLATFORM_SPI_IMX
+	select IMX_HAVE_PLATFORM_IMX_I2C
+	select IMX_HAVE_PLATFORM_VIV_GPU
+	select IMX_HAVE_PLATFORM_IMX_VPU
+	select IMX_HAVE_PLATFORM_IMX_DVFS
+	select IMX_HAVE_PLATFORM_IMX_ANATOP_THERMAL
+	select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+	select IMX_HAVE_PLATFORM_MXC_EHCI
+	select IMX_HAVE_PLATFORM_FSL_OTG
+	select IMX_HAVE_PLATFORM_FSL_USB_WAKEUP
+	select IMX_HAVE_PLATFORM_AHCI
+	select IMX_HAVE_PLATFORM_IMX_OCOTP
+	select IMX_HAVE_PLATFORM_IMX_VIIM
+	select IMX_HAVE_PLATFORM_IMX2_WDT
+	select IMX_HAVE_PLATFORM_IMX_SNVS_RTC
+	select IMX_HAVE_PLATFORM_IMX_PM
+	select IMX_HAVE_PLATFORM_MXC_HDMI
+	select IMX_HAVE_PLATFORM_IMX_PCIE
+	help
+	  Include support for i.MX 6Quad HDMI Dongle platform. This includes specific
+	  configurations for the board and its peripherals.
+
 comment "MX6 Options:"
 
 config IMX_PCIE
diff --git a/arch/arm/mach-mx6/Makefile b/arch/arm/mach-mx6/Makefile
index c929f2e56cfc..d39aa2945319 100644
--- a/arch/arm/mach-mx6/Makefile
+++ b/arch/arm/mach-mx6/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_MACH_MX6SL_EVK) += board-mx6sl_evk.o mx6sl_evk_pmic_pfuze100.o
 obj-$(CONFIG_MACH_MX6Q_SABRELITE) += board-mx6q_sabrelite.o
 obj-$(CONFIG_MACH_MX6Q_SABRESD) += board-mx6q_sabresd.o mx6q_sabresd_pmic_pfuze100.o
 obj-$(CONFIG_MACH_MX6Q_SABREAUTO) += board-mx6q_sabreauto.o mx6q_sabreauto_pmic_pfuze100.o
+obj-$(CONFIG_MACH_MX6Q_HDMIDONGLE) += board-mx6q_hdmidongle.o mx6q_hdmidongle_pmic_wm831x.o
 obj-$(CONFIG_SMP) += plat_hotplug.o platsmp.o headsmp.o
 obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
 obj-$(CONFIG_IMX_PCIE) += pcie.o
diff --git a/arch/arm/mach-mx6/board-mx6dl_hdmidongle.h b/arch/arm/mach-mx6/board-mx6dl_hdmidongle.h
new file mode 100644
index 000000000000..8f8c9e47acc5
--- /dev/null
+++ b/arch/arm/mach-mx6/board-mx6dl_hdmidongle.h
@@ -0,0 +1,336 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef _BOARD_MX6DL_HDMIDONGLE_H
+#define _BOARD_MX6DL_HDMIDONGLE_H
+#include <mach/iomux-mx6dl.h>
+
+static iomux_v3_cfg_t mx6dl_hdmidongle_rev_a_pads[] = {
+	/* SPI2 for PMIC communication port */
+	MX6DL_PAD_EIM_OE__ECSPI2_MISO,
+	MX6DL_PAD_EIM_RW__ECSPI2_SS0,
+	MX6DL_PAD_EIM_CS0__ECSPI2_SCLK,
+	MX6DL_PAD_EIM_CS1__ECSPI2_MOSI,
+
+	/*USB_OTG_DET(USB OTG cable plug detect) */
+	MX6DL_PAD_EIM_A16__GPIO_2_22,
+	/*BT_WAKEUP_HOST(Combo module BT wake-up output) */
+	MX6DL_PAD_EIM_A25__GPIO_5_2,
+	/* HOST_WAKEUP_BT(CPU wakeup BT signal)*/
+	MX6DL_PAD_EIM_D16__GPIO_3_16,
+
+	/* I2C3  */
+	MX6DL_PAD_EIM_D17__I2C3_SCL,
+	MX6DL_PAD_EIM_D18__I2C3_SDA,
+
+	/* USB OC pin */
+	MX6DL_PAD_EIM_D21__USBOH3_USBOTG_OC,
+	/* WLAN_WAKEUP_HOST(Combo module WLAN host wake-up output) */
+	MX6DL_PAD_EIM_D22__GPIO_3_22,
+
+	/* BT_UART2  */
+	MX6DL_PAD_EIM_D26__UART2_TXD,
+	MX6DL_PAD_EIM_D27__UART2_RXD,
+	MX6DL_PAD_EIM_D28__UART2_CTS,
+	MX6DL_PAD_EIM_D29__UART2_RTS,
+
+	/*BT_nRST(Combo module BT reset signal)*/
+	MX6DL_PAD_EIM_DA7__GPIO_3_7,
+
+	/*BT_REG_ON(Combo module BT Internal regulators power enable/disable)*/
+	MX6DL_PAD_EIM_DA9__GPIO_3_9,
+
+	/*WL_REG_ON(Combo module WLAN Internal regulators power enable/disable)*/
+	MX6DL_PAD_EIM_DA10__GPIO_3_10,
+
+	/* GPIO2 */
+	MX6DL_PAD_EIM_A22__GPIO_2_16,	/* Boot Mode Select */
+	MX6DL_PAD_EIM_A21__GPIO_2_17,	/* Boot Mode Select */
+	MX6DL_PAD_EIM_A20__GPIO_2_18,	/* Boot Mode Select */
+	MX6DL_PAD_EIM_A19__GPIO_2_19,	/* Boot Mode Select */
+	MX6DL_PAD_EIM_A18__GPIO_2_20,	/* Boot Mode Select */
+	MX6DL_PAD_EIM_A17__GPIO_2_21,	/* Boot Mode Select */
+	MX6DL_PAD_EIM_RW__GPIO_2_26,		/* Boot Mode Select */
+	MX6DL_PAD_EIM_LBA__GPIO_2_27,	/* Boot Mode Select */
+	MX6DL_PAD_EIM_EB0__GPIO_2_28,	/* Boot Mode Select */
+	MX6DL_PAD_EIM_EB1__GPIO_2_29,	/* Boot Mode Select */
+	MX6DL_PAD_EIM_EB2__GPIO_2_30,	/* Boot Mode Select */
+	MX6DL_PAD_EIM_EB3__GPIO_2_31,	/* Boot Mode Select */
+
+	/* GPIO3 */
+	MX6DL_PAD_EIM_DA0__GPIO_3_0,	/*  Boot Mode Select */
+	MX6DL_PAD_EIM_DA1__GPIO_3_1,	/*  Boot Mode Select */
+	MX6DL_PAD_EIM_DA2__GPIO_3_2,	/*  Boot Mode Select */
+	MX6DL_PAD_EIM_DA3__GPIO_3_3,	/*  Boot Mode Select */
+	MX6DL_PAD_EIM_DA4__GPIO_3_4,	/*  Boot Mode Select */
+	MX6DL_PAD_EIM_DA5__GPIO_3_5,	/*  Boot Mode Select */
+	MX6DL_PAD_EIM_DA6__GPIO_3_6,	/*  Boot Mode Select */
+	MX6DL_PAD_EIM_DA8__GPIO_3_8,	/*  Boot Mode Select */
+	MX6DL_PAD_EIM_DA11__GPIO_3_11,	/*  Boot Mode Select */
+	MX6DL_PAD_EIM_DA12__GPIO_3_12,	/*  Boot Mode Select */
+	MX6DL_PAD_EIM_DA13__GPIO_3_13,	/*  Boot Mode Select */
+	MX6DL_PAD_EIM_DA14__GPIO_3_14,	/*  Boot Mode Select */
+	MX6DL_PAD_EIM_DA15__GPIO_3_15,	/*  Boot Mode Select */
+
+	/* GPIO5 */
+	MX6DL_PAD_EIM_WAIT__GPIO_5_0,	/* Boot Mode Select */
+	MX6DL_PAD_EIM_A24__GPIO_5_4,	/* Boot Mode Select */
+
+	/* GPIO6 */
+	MX6DL_PAD_EIM_A23__GPIO_6_6,	/* Boot Mode Select */
+
+	/* I2C1  */
+	MX6DL_PAD_CSI0_DAT8__I2C1_SDA,
+	MX6DL_PAD_CSI0_DAT9__I2C1_SCL,
+
+	/* UART1 for debug */
+	MX6DL_PAD_CSI0_DAT10__UART1_TXD,
+	MX6DL_PAD_CSI0_DAT11__UART1_RXD,
+
+	/* SD1 (Combo module WLAN SDIO )*/
+	MX6DL_PAD_SD1_CLK__USDHC1_CLK,
+	MX6DL_PAD_SD1_CMD__USDHC1_CMD,
+	MX6DL_PAD_SD1_DAT0__USDHC1_DAT0,
+	MX6DL_PAD_SD1_DAT1__USDHC1_DAT1,
+	MX6DL_PAD_SD1_DAT2__USDHC1_DAT2,
+	MX6DL_PAD_SD1_DAT3__USDHC1_DAT3,
+
+	/* SD2 (MicroSD SDIO CMD)*/
+	MX6DL_PAD_SD2_CLK__USDHC2_CLK,
+	MX6DL_PAD_SD2_CMD__USDHC2_CMD,
+	MX6DL_PAD_SD2_DAT0__USDHC2_DAT0,
+	MX6DL_PAD_SD2_DAT1__USDHC2_DAT1,
+	MX6DL_PAD_SD2_DAT2__USDHC2_DAT2,
+	MX6DL_PAD_SD2_DAT3__USDHC2_DAT3,
+	/*SD_DET (SD plug-in detect interrupt)*/
+	MX6DL_PAD_GPIO_4__GPIO_1_4,
+
+	/* SD3 (eMMC SDIO)*/
+	MX6DL_PAD_SD3_CLK__USDHC3_CLK_50MHZ,
+	MX6DL_PAD_SD3_CMD__USDHC3_CMD_50MHZ,
+	MX6DL_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ,
+	MX6DL_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ,
+	MX6DL_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ,
+	MX6DL_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ,
+	MX6DL_PAD_SD3_DAT4__USDHC3_DAT4_50MHZ,
+	MX6DL_PAD_SD3_DAT5__USDHC3_DAT5_50MHZ,
+	MX6DL_PAD_SD3_DAT6__USDHC3_DAT6_50MHZ,
+	MX6DL_PAD_SD3_DAT7__USDHC3_DAT7_50MHZ,
+	MX6DL_PAD_SD3_RST__USDHC3_RST,
+
+	/* UART4 for debug */
+	MX6DL_PAD_KEY_COL0__UART4_TXD,
+	MX6DL_PAD_KEY_ROW0__UART4_RXD,
+
+	/* I2C2 */
+	MX6DL_PAD_KEY_COL3__I2C2_SCL,	/* GPIO4[12] */
+	MX6DL_PAD_KEY_ROW3__I2C2_SDA,	/* GPIO4[13] */
+
+	/*DCDC5V_PWREN(5V DCDC BOOST control signal)*/
+	MX6DL_PAD_KEY_COL4__GPIO_4_14,
+
+	/*USB_OTG_PWREN(USB OTG power change control signal)*/
+	MX6DL_PAD_KEY_ROW4__GPIO_4_15,
+
+	/* USBOTG ID pin */
+	MX6DL_PAD_GPIO_1__USBOTG_ID,
+
+	/* I2C3 */
+	MX6DL_PAD_GPIO_5__I2C3_SCL,
+	MX6DL_PAD_GPIO_16__I2C3_SDA,
+
+	/*WDOG(Watch dog output)*/
+	MX6DL_PAD_GPIO_9__GPIO_1_9,
+
+	/*PMIC_nINT(PMIC interrupt signal)*/
+	MX6DL_PAD_NANDF_CS0__GPIO_6_11,
+
+	/*GPIO_nRST(GPIO shutdown control)*/
+	MX6DL_PAD_NANDF_CS1__GPIO_6_14,
+
+	/*PWRKEY_DET(Power key press detection)*/
+	MX6DL_PAD_NANDF_CS3__GPIO_6_16,
+
+	/*CHG_SYS_ON(Charger auto power on control signal)*/
+	MX6DL_PAD_NANDF_D6__GPIO_2_6,
+
+	/*IR_RC*/
+	MX6DL_PAD_SD4_DAT6__GPIO_2_14,
+};
+
+static iomux_v3_cfg_t mx6dl_hdmidongle_rev_b_pads[] = {
+	/* SPI2 for PMIC communication port */
+	MX6DL_PAD_EIM_OE__ECSPI2_MISO,
+	MX6DL_PAD_EIM_RW__ECSPI2_SS0,
+	MX6DL_PAD_EIM_CS0__ECSPI2_SCLK,
+	MX6DL_PAD_EIM_CS1__ECSPI2_MOSI,
+
+	/*USB_OTG_DET(USB OTG cable plug detect) */
+	MX6DL_PAD_EIM_A16__GPIO_2_22,
+	/*WLAN_CLKREQn*/
+	MX6DL_PAD_EIM_A25__GPIO_5_2,
+
+	/* WLAN_ACT */
+	MX6DL_PAD_EIM_D17__GPIO_3_17,
+
+	/*BT_PERI*/
+	MX6DL_PAD_EIM_D18__GPIO_3_18,
+
+	/* USB OC pin */
+	MX6DL_PAD_EIM_D21__USBOH3_USBOTG_OC,
+
+	/* WLAN_WAKEn (PM event, OD, used to reactivate the PCIe main PWR and REF CLK) */
+	MX6DL_PAD_EIM_D22__GPIO_3_22,
+
+
+	/*WLAN_PERSTn (PCIe rst signal, avtive LOW)*/
+	MX6DL_PAD_EIM_DA9__GPIO_3_9,
+
+	/*WLAN_PDn (Externally shutdown RTL8192)*/
+	MX6DL_PAD_EIM_DA10__GPIO_3_10,
+
+	/* GPIO2 */
+	MX6DL_PAD_EIM_A22__GPIO_2_16,	/* Boot Mode Select */
+	MX6DL_PAD_EIM_A21__GPIO_2_17,	/* Boot Mode Select */
+	MX6DL_PAD_EIM_A20__GPIO_2_18,	/* Boot Mode Select */
+	MX6DL_PAD_EIM_A19__GPIO_2_19,	/* Boot Mode Select */
+	MX6DL_PAD_EIM_A18__GPIO_2_20,	/* Boot Mode Select */
+	MX6DL_PAD_EIM_A17__GPIO_2_21,	/* Boot Mode Select */
+	MX6DL_PAD_EIM_RW__GPIO_2_26,		/* Boot Mode Select */
+	MX6DL_PAD_EIM_LBA__GPIO_2_27,	/* Boot Mode Select */
+	MX6DL_PAD_EIM_EB0__GPIO_2_28,	/* Boot Mode Select */
+	MX6DL_PAD_EIM_EB1__GPIO_2_29,	/* Boot Mode Select */
+	MX6DL_PAD_EIM_EB2__GPIO_2_30,	/* Boot Mode Select */
+	MX6DL_PAD_EIM_EB3__GPIO_2_31,	/* Boot Mode Select */
+
+	/* GPIO3 */
+	MX6DL_PAD_EIM_DA0__GPIO_3_0,	/*  Boot Mode Select */
+	MX6DL_PAD_EIM_DA1__GPIO_3_1,	/*  Boot Mode Select */
+	MX6DL_PAD_EIM_DA2__GPIO_3_2,	/*  Boot Mode Select */
+	MX6DL_PAD_EIM_DA3__GPIO_3_3,	/*  Boot Mode Select */
+	MX6DL_PAD_EIM_DA4__GPIO_3_4,	/*  Boot Mode Select */
+	MX6DL_PAD_EIM_DA5__GPIO_3_5,	/*  Boot Mode Select */
+	MX6DL_PAD_EIM_DA6__GPIO_3_6,	/*  Boot Mode Select */
+	MX6DL_PAD_EIM_DA8__GPIO_3_8,	/*  Boot Mode Select */
+	MX6DL_PAD_EIM_DA11__GPIO_3_11,	/*  Boot Mode Select */
+	MX6DL_PAD_EIM_DA12__GPIO_3_12,	/*  Boot Mode Select */
+	MX6DL_PAD_EIM_DA13__GPIO_3_13,	/*  Boot Mode Select */
+	MX6DL_PAD_EIM_DA14__GPIO_3_14,	/*  Boot Mode Select */
+	MX6DL_PAD_EIM_DA15__GPIO_3_15,	/*  Boot Mode Select */
+
+	/* GPIO5 */
+	MX6DL_PAD_EIM_WAIT__GPIO_5_0,	/* Boot Mode Select */
+	MX6DL_PAD_EIM_A24__GPIO_5_4,		/* Boot Mode Select */
+
+	/* GPIO6 */
+	MX6DL_PAD_EIM_A23__GPIO_6_6,	/* Boot Mode Select */
+
+	/* SD2 (MicroSD SDIO CMD)*/
+	MX6DL_PAD_SD2_CLK__USDHC2_CLK,
+	MX6DL_PAD_SD2_CMD__USDHC2_CMD,
+	MX6DL_PAD_SD2_DAT0__USDHC2_DAT0,
+	MX6DL_PAD_SD2_DAT1__USDHC2_DAT1,
+	MX6DL_PAD_SD2_DAT2__USDHC2_DAT2,
+	MX6DL_PAD_SD2_DAT3__USDHC2_DAT3,
+	/*SD_DET (SD plug-in detect interrupt)*/
+	MX6DL_PAD_GPIO_4__GPIO_1_4,
+
+	/* SD3 (eMMC SDIO)*/
+	MX6DL_PAD_SD3_CLK__USDHC3_CLK_50MHZ,
+	MX6DL_PAD_SD3_CMD__USDHC3_CMD_50MHZ,
+	MX6DL_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ,
+	MX6DL_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ,
+	MX6DL_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ,
+	MX6DL_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ,
+	MX6DL_PAD_SD3_DAT4__USDHC3_DAT4_50MHZ,
+	MX6DL_PAD_SD3_DAT5__USDHC3_DAT5_50MHZ,
+	MX6DL_PAD_SD3_DAT6__USDHC3_DAT6_50MHZ,
+	MX6DL_PAD_SD3_DAT7__USDHC3_DAT7_50MHZ,
+	MX6DL_PAD_SD3_RST__USDHC3_RST,
+
+	/* UART4 for debug */
+	MX6DL_PAD_KEY_COL0__UART4_TXD,
+	MX6DL_PAD_KEY_ROW0__UART4_RXD,
+
+	/*SD2_VSELECT (SD2 SDXC power exchange control signal)*/
+	MX6DL_PAD_KEY_ROW1__GPIO_4_9,
+
+	/*PWRKEY_DET (Pwr button detection interrupt)*/
+	MX6DL_PAD_ENET_RXD0__GPIO_1_27,
+
+	/*USB_OTG_PWREN(USB OTG power change control signal)*/
+	MX6DL_PAD_KEY_ROW4__GPIO_4_15,
+
+	/* USBOTG ID pin */
+	MX6DL_PAD_GPIO_1__USBOTG_ID,
+
+	/* I2C2 */
+	MX6DL_PAD_KEY_COL3__I2C2_SCL,	/* GPIO4[12] */
+	MX6DL_PAD_KEY_ROW3__I2C2_SDA,	/* GPIO4[13] */
+
+	/* I2C3 */
+	MX6DL_PAD_GPIO_5__I2C3_SCL,
+	MX6DL_PAD_GPIO_16__I2C3_SDA,
+
+	/*WDOG(Watch dog output)*/
+	MX6DL_PAD_GPIO_9__GPIO_1_9,
+
+	/*PMIC_nINT(PMIC interrupt signal)*/
+	MX6DL_PAD_SD4_DAT3__GPIO_2_11,
+
+	/*GPIO_nRST(GPIO shutdown control)*/
+	MX6DL_PAD_SD4_DAT1__GPIO_2_9,
+
+	/*CHG_SYS_ON(Charger auto power on control signal)*/
+	MX6DL_PAD_SD4_DAT6__GPIO_2_14,
+};
+
+/* The GPMI is conflicted with SD3, so init this in the driver. */
+static iomux_v3_cfg_t mx6dl_gpmi_nand[] __initdata = {
+	MX6DL_PAD_NANDF_CLE__RAWNAND_CLE,
+	MX6DL_PAD_NANDF_ALE__RAWNAND_ALE,
+	MX6DL_PAD_NANDF_CS0__RAWNAND_CE0N,
+	MX6DL_PAD_NANDF_CS1__RAWNAND_CE1N,
+	MX6DL_PAD_NANDF_CS2__RAWNAND_CE2N,
+	MX6DL_PAD_NANDF_CS3__RAWNAND_CE3N,
+	MX6DL_PAD_NANDF_RB0__RAWNAND_READY0,
+	MX6DL_PAD_SD4_DAT0__RAWNAND_DQS,
+	MX6DL_PAD_NANDF_D0__RAWNAND_D0,
+	MX6DL_PAD_NANDF_D1__RAWNAND_D1,
+	MX6DL_PAD_NANDF_D2__RAWNAND_D2,
+	MX6DL_PAD_NANDF_D3__RAWNAND_D3,
+	MX6DL_PAD_NANDF_D4__RAWNAND_D4,
+	MX6DL_PAD_NANDF_D5__RAWNAND_D5,
+	MX6DL_PAD_NANDF_D6__RAWNAND_D6,
+	MX6DL_PAD_NANDF_D7__RAWNAND_D7,
+	MX6DL_PAD_SD4_CMD__RAWNAND_RDN,
+	MX6DL_PAD_SD4_CLK__RAWNAND_WRN,
+	MX6DL_PAD_NANDF_WP_B__RAWNAND_RESETN,
+};
+
+static iomux_v3_cfg_t mx6dl_hdmidongle_hdmi_ddc_pads[] = {
+	MX6DL_PAD_KEY_COL3__HDMI_TX_DDC_SCL, /* HDMI DDC SCL */
+	MX6DL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA, /* HDMI DDC SDA */
+};
+
+static iomux_v3_cfg_t mx6dl_hdmidongle_i2c2_pads[] = {
+	MX6DL_PAD_KEY_COL3__I2C2_SCL,	/* I2C2 SCL */
+	MX6DL_PAD_KEY_ROW3__I2C2_SDA,	/* I2C2 SDA */
+};
+
+#endif
diff --git a/arch/arm/mach-mx6/board-mx6q_hdmidongle.c b/arch/arm/mach-mx6/board-mx6q_hdmidongle.c
new file mode 100644
index 000000000000..98d05bc0a3cb
--- /dev/null
+++ b/arch/arm/mach-mx6/board-mx6q_hdmidongle.c
@@ -0,0 +1,699 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/types.h>
+#include <linux/sched.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/init.h>
+#include <linux/input.h>
+#include <linux/nodemask.h>
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/fsl_devices.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+#include <linux/i2c.h>
+#include <linux/i2c/pca953x.h>
+#include <linux/ata.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/partitions.h>
+#include <linux/regulator/consumer.h>
+#include <linux/pmic_external.h>
+#include <linux/pmic_status.h>
+#include <linux/ipu.h>
+#include <linux/mxcfb.h>
+#include <linux/pwm_backlight.h>
+#include <linux/fec.h>
+#include <linux/memblock.h>
+#include <linux/gpio.h>
+#include <linux/ion.h>
+#include <linux/etherdevice.h>
+#include <linux/regulator/anatop-regulator.h>
+#include <linux/regulator/consumer.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/mfd/mxc-hdmi-core.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/mxc_dvfs.h>
+#include <mach/memory.h>
+#include <mach/iomux-mx6q.h>
+#include <mach/imx-uart.h>
+#include <mach/viv_gpu.h>
+#include <mach/ipu-v3.h>
+#include <mach/mxc_hdmi.h>
+
+#include <asm/irq.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/common.h>
+
+#ifdef CONFIG_IMX_PCIE
+#include <linux/wakelock.h>
+#endif
+
+#include "usb.h"
+#include "devices-imx6q.h"
+#include "crm_regs.h"
+#include "cpu_op-mx6.h"
+#include "board-mx6q_hdmidongle.h"
+#include "board-mx6dl_hdmidongle.h"
+
+#define HDMIDONGLE_USB_OTG_PWR	IMX_GPIO_NR(4, 15)
+#define HDMIDONGLE_USB_H1_PWR	IMX_GPIO_NR(4, 14)
+#define HDMIDONGLE_ECSPI2_CS0  IMX_GPIO_NR(2, 26)
+#define HDMIDONGLE_HDMI_CEC_IN	IMX_GPIO_NR(4, 11)
+
+
+#define HDMIDONGLE_BT_RST	IMX_GPIO_NR(3, 7)
+#define HDMIDONGLE_BT_EN	IMX_GPIO_NR(3, 9)
+#define HDMIDONGLE_WL_EN        IMX_GPIO_NR(3, 10)
+
+#define HDMIDONGLE_SD2_CD		IMX_GPIO_NR(1, 4)
+#define HDMIDONGLE_REVA_POWER_KEY	IMX_GPIO_NR(6, 16)
+#define HDMIDONGLE_REVB_POWER_KEY	IMX_GPIO_NR(1, 27)
+
+#ifdef CONFIG_IMX_PCIE
+#define HDMIDONGLE_PCIE_PWR_EN	IMX_GPIO_NR(3, 7) /*fake pcie power enable */
+#define HDMIDONGLE_PCIE_RST 	IMX_GPIO_NR(3, 9)
+#define HDMIDONGLE_PCIE_WAKE	IMX_GPIO_NR(3, 22)
+#define HDMIDONGLE_PCIE_DIS		IMX_GPIO_NR(3, 10)
+static struct wake_lock pcie_wake_lock;
+#endif
+
+extern char *gp_reg_id;
+extern char *soc_reg_id;
+extern char *pu_reg_id;
+
+static const struct esdhc_platform_data mx6q_hdmidongle_sd1_data __initconst = {
+	.always_present = 1,
+};
+
+static const struct esdhc_platform_data mx6q_hdmidongle_sd2_data __initconst = {
+	.cd_gpio = HDMIDONGLE_SD2_CD,
+	.keep_power_at_suspend = 1,
+	.support_8bit = 0,
+	.delay_line = 0,
+	.cd_type = ESDHC_CD_CONTROLLER,
+};
+
+static const struct esdhc_platform_data mx6q_hdmidongle_sd3_data __initconst = {
+	.always_present = 1,
+	.keep_power_at_suspend = 1,
+	.support_8bit = 1,
+	.delay_line = 0,
+	.cd_type = ESDHC_CD_PERMANENT,
+};
+
+static const struct esdhc_platform_data mx6q_hdmidongle_revc_sd3_data __initconst = {
+	.always_present = 1,
+	.keep_power_at_suspend = 1,
+	.support_8bit = 0,
+	.delay_line = 0,
+	.cd_type = ESDHC_CD_PERMANENT,
+};
+
+
+static int __init gpmi_nand_platform_init(void)
+{
+	iomux_v3_cfg_t *nand_pads = NULL;
+	u32 nand_pads_cnt;
+
+	if (cpu_is_mx6q()) {
+		nand_pads = mx6q_gpmi_nand;
+		nand_pads_cnt = ARRAY_SIZE(mx6q_gpmi_nand);
+	} else if (cpu_is_mx6dl()) {
+		nand_pads = mx6dl_gpmi_nand;
+		nand_pads_cnt = ARRAY_SIZE(mx6dl_gpmi_nand);
+
+	}
+	BUG_ON(!nand_pads);
+	return mxc_iomux_v3_setup_multiple_pads(nand_pads, nand_pads_cnt);
+}
+
+static struct gpmi_nand_platform_data
+mx6_gpmi_nand_platform_data __initdata = {
+	.platform_init           = gpmi_nand_platform_init,
+	.min_prop_delay_in_ns    = 5,
+	.max_prop_delay_in_ns    = 9,
+	.max_chip_count          = 1,
+	.enable_bbt              = 1,
+	.enable_ddr              = 0,
+};
+
+static int __init board_support_onfi_nand(char *p)
+{
+	mx6_gpmi_nand_platform_data.enable_ddr = 1;
+	return 0;
+}
+
+early_param("onfi_support", board_support_onfi_nand);
+
+
+static const struct anatop_thermal_platform_data
+	mx6q_hdmidongle_anatop_thermal_data __initconst = {
+		.name = "anatop_thermal",
+};
+
+static inline void mx6q_hdmidongle_init_uart(void)
+{
+	if (board_is_mx6_reva())
+		imx6q_add_imx_uart(1, NULL);
+	imx6q_add_imx_uart(0, NULL);
+	imx6q_add_imx_uart(3, NULL);
+}
+
+static struct imxi2c_platform_data mx6q_hdmidongle_i2c_data = {
+	.bitrate = 100000,
+};
+
+static struct i2c_board_info mxc_i2c1_board_info[] __initdata = {
+	{
+		I2C_BOARD_INFO("mxc_hdmi_i2c", 0x50),
+	},
+};
+
+
+static void imx6q_hdmidongle_usbotg_vbus(bool on)
+{
+	if (on)
+		gpio_set_value(HDMIDONGLE_USB_OTG_PWR, 1);
+	else
+		gpio_set_value(HDMIDONGLE_USB_OTG_PWR, 0);
+}
+
+static void __init imx6q_hdmidongle_init_usb(void)
+{
+	int ret = 0;
+
+	imx_otg_base = MX6_IO_ADDRESS(MX6Q_USB_OTG_BASE_ADDR);
+	/* disable external charger detect,
+	 * or it will affect signal quality at dp .
+	 */
+	ret = gpio_request(HDMIDONGLE_USB_OTG_PWR, "usb-pwr");
+	if (ret) {
+		pr_err("failed to get GPIO HDMIDONGLE_USB_OTG_PWR: %d\n",
+			ret);
+		return;
+	}
+	gpio_direction_output(HDMIDONGLE_USB_OTG_PWR, 0);
+	/* keep USB host1 VBUS always on */
+	if (board_is_mx6_reva()) {
+		ret = gpio_request(HDMIDONGLE_USB_H1_PWR, "usb-h1-pwr");
+		if (ret) {
+			pr_err("failed to get GPIO HDMIDONGLE_USB_H1_PWR: %d\n",
+				ret);
+			return;
+		}
+		gpio_direction_output(HDMIDONGLE_USB_H1_PWR, 1);
+	}
+	mxc_iomux_set_gpr_register(1, 13, 1, 1);
+
+	mx6_set_otghost_vbus_func(imx6q_hdmidongle_usbotg_vbus);
+}
+
+
+static struct viv_gpu_platform_data imx6q_gpu_pdata __initdata = {
+	.reserved_mem_size = SZ_128M + SZ_64M,
+};
+
+
+static struct ipuv3_fb_platform_data hdmidongle_fb_data[] = {
+	{/*fb0*/
+	.disp_dev = "hdmi",
+	.interface_pix_fmt = IPU_PIX_FMT_RGB24,
+	.mode_str = "1920x1080M@60",
+	.default_bpp = 32,
+	.int_clk = false,
+	},
+};
+
+static void hdmi_init(int ipu_id, int disp_id)
+{
+	int hdmi_mux_setting;
+
+	if ((ipu_id > 1) || (ipu_id < 0)) {
+		pr_err("Invalid IPU select for HDMI: %d. Set to 0\n", ipu_id);
+		ipu_id = 0;
+	}
+
+	if ((disp_id > 1) || (disp_id < 0)) {
+		pr_err("Invalid DI select for HDMI: %d. Set to 0\n", disp_id);
+		disp_id = 0;
+	}
+
+	/* Configure the connection between IPU1/2 and HDMI */
+	hdmi_mux_setting = 2*ipu_id + disp_id;
+
+	/* GPR3, bits 2-3 = HDMI_MUX_CTL */
+	mxc_iomux_set_gpr_register(3, 2, 2, hdmi_mux_setting);
+	/* Set HDMI event as SDMA event2 while Chip version later than TO1.2 */
+	if (hdmi_SDMA_check())
+		mxc_iomux_set_gpr_register(0, 0, 1, 1);
+}
+
+/* On mx6x sabresd board i2c2 iomux with hdmi ddc,
+ * the pins default work at i2c2 function,
+ when hdcp enable, the pins should work at ddc function */
+
+static void hdmi_enable_ddc_pin(void)
+{
+	if (cpu_is_mx6dl())
+		mxc_iomux_v3_setup_multiple_pads(mx6dl_hdmidongle_hdmi_ddc_pads,
+			ARRAY_SIZE(mx6dl_hdmidongle_hdmi_ddc_pads));
+	else
+		mxc_iomux_v3_setup_multiple_pads(mx6q_hdmidongle_hdmi_ddc_pads,
+			ARRAY_SIZE(mx6q_hdmidongle_hdmi_ddc_pads));
+}
+
+static void hdmi_disable_ddc_pin(void)
+{
+	if (cpu_is_mx6dl())
+		mxc_iomux_v3_setup_multiple_pads(mx6dl_hdmidongle_i2c2_pads,
+			ARRAY_SIZE(mx6dl_hdmidongle_i2c2_pads));
+	else
+		mxc_iomux_v3_setup_multiple_pads(mx6q_hdmidongle_i2c2_pads,
+			ARRAY_SIZE(mx6q_hdmidongle_i2c2_pads));
+}
+
+
+static struct fsl_mxc_hdmi_platform_data hdmi_data = {
+	.init = hdmi_init,
+	.enable_pins = hdmi_enable_ddc_pin,
+	.disable_pins = hdmi_disable_ddc_pin,
+};
+
+static struct fsl_mxc_hdmi_core_platform_data hdmi_core_data = {
+	.ipu_id = 0,
+	.disp_id = 0,
+};
+
+static struct imx_ipuv3_platform_data ipu_data[] = {
+	{
+	.rev = 4,
+	.csi_clk[0] = "clko_clk",
+	}, {
+	.rev = 4,
+	.csi_clk[0] = "clko_clk",
+	},
+};
+
+static struct ion_platform_data imx_ion_data = {
+	.nr = 1,
+	.heaps = {
+		{
+		.id = 0,
+		.type = ION_HEAP_TYPE_CARVEOUT,
+		.name = "vpu_ion",
+		.size = SZ_64M,
+		},
+	},
+};
+
+static void hdmidongle_suspend_enter(void)
+{
+	/* suspend preparation */
+}
+
+static void hdmidongle_suspend_exit(void)
+{
+	/* resume restore */
+}
+static const struct pm_platform_data mx6q_hdmidongle_pm_data __initconst = {
+	.name = "imx_pm",
+	.suspend_enter = hdmidongle_suspend_enter,
+	.suspend_exit = hdmidongle_suspend_exit,
+};
+
+static struct regulator_consumer_supply hdmidongle_vmmc_consumers[] = {
+	REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.1"),
+	REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.2"),
+	REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.3"),
+};
+
+static struct regulator_init_data hdmidongle_vmmc_init = {
+	.num_consumer_supplies = ARRAY_SIZE(hdmidongle_vmmc_consumers),
+	.consumer_supplies = hdmidongle_vmmc_consumers,
+};
+
+static struct fixed_voltage_config hdmidongle_vmmc_reg_config = {
+	.supply_name		= "vmmc",
+	.microvolts		= 3300000,
+	.gpio			= -1,
+	.init_data		= &hdmidongle_vmmc_init,
+};
+
+static struct platform_device hdmidongle_vmmc_reg_devices = {
+	.name	= "reg-fixed-voltage",
+	.id	= 3,
+	.dev	= {
+		.platform_data = &hdmidongle_vmmc_reg_config,
+	},
+};
+
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake, debounce)	\
+{								\
+	.gpio		= gpio_num,				\
+	.type		= EV_KEY,				\
+	.code		= ev_code,				\
+	.active_low	= act_low,				\
+	.desc		= "btn " descr,				\
+	.wakeup		= wake,					\
+	.debounce_interval = debounce,				\
+}
+
+static struct gpio_keys_button hdmidongle_reva_buttons[] = {
+	GPIO_BUTTON(HDMIDONGLE_REVA_POWER_KEY, KEY_POWER, 1, "power", 1, 1),
+};
+
+static struct gpio_keys_platform_data hdmidongle_reva_button_data = {
+	.buttons	= hdmidongle_reva_buttons,
+	.nbuttons	= ARRAY_SIZE(hdmidongle_reva_buttons),
+};
+
+static struct platform_device hdmidongle_reva_button_device = {
+	.name		= "gpio-keys",
+	.id		= -1,
+	.num_resources  = 0,
+	.dev		= {
+		.platform_data = &hdmidongle_reva_button_data,
+	}
+};
+
+static struct gpio_keys_button hdmidongle_revb_buttons[] = {
+	GPIO_BUTTON(HDMIDONGLE_REVB_POWER_KEY, KEY_POWER, 1, "power", 1, 1),
+};
+
+static struct gpio_keys_platform_data hdmidongle_revb_button_data = {
+	.buttons	= hdmidongle_revb_buttons,
+	.nbuttons	= ARRAY_SIZE(hdmidongle_revb_buttons),
+};
+
+static struct platform_device hdmidongle_revb_button_device = {
+	.name		= "gpio-keys",
+	.id		= -1,
+	.num_resources  = 0,
+	.dev		= {
+		.platform_data = &hdmidongle_revb_button_data,
+	}
+};
+
+
+static void __init imx6q_add_device_buttons(void)
+{
+	if (board_is_mx6_reva())
+		platform_device_register(&hdmidongle_reva_button_device);
+	else
+		platform_device_register(&hdmidongle_revb_button_device);
+}
+#else
+static void __init imx6q_add_device_buttons(void) {}
+#endif
+
+static struct mxc_dvfs_platform_data hdmidongle_dvfscore_data = {
+	#ifdef CONFIG_MX6_INTER_LDO_BYPASS
+	.reg_id = "VDDCORE",
+	#else
+	.reg_id = "cpu_vddgp",
+	.soc_id = "cpu_vddsoc",
+	.pu_id = "cpu_vddvpu",
+	#endif
+	.clk1_id = "cpu_clk",
+	.clk2_id = "gpc_dvfs_clk",
+	.gpc_cntr_offset = MXC_GPC_CNTR_OFFSET,
+	.ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET,
+	.ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET,
+	.ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET,
+	.prediv_mask = 0x1F800,
+	.prediv_offset = 11,
+	.prediv_val = 3,
+	.div3ck_mask = 0xE0000000,
+	.div3ck_offset = 29,
+	.div3ck_val = 2,
+	.emac_val = 0x08,
+	.upthr_val = 25,
+	.dnthr_val = 9,
+	.pncthr_val = 33,
+	.upcnt_val = 10,
+	.dncnt_val = 10,
+	.delay_time = 80,
+};
+
+static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags,
+				   char **cmdline, struct meminfo *mi)
+{
+	char *str;
+	struct tag *t;
+	int i = 0;
+	struct ipuv3_fb_platform_data *pdata_fb = hdmidongle_fb_data;
+
+	for_each_tag(t, tags) {
+		if (t->hdr.tag == ATAG_CMDLINE) {
+			str = t->u.cmdline.cmdline;
+			str = strstr(str, "fbmem=");
+			if (str != NULL) {
+				str += 6;
+				pdata_fb[i++].res_size[0] = memparse(str, &str);
+				while (*str == ',' &&
+					i < ARRAY_SIZE(hdmidongle_fb_data)) {
+					str++;
+					pdata_fb[i++].res_size[0] = memparse(str, &str);
+				}
+			}
+			break;
+		}
+	}
+}
+
+#define SNVS_LPCR 0x38
+static void mx6_snvs_poweroff(void)
+{
+
+	void __iomem *mx6_snvs_base =  MX6_IO_ADDRESS(MX6Q_SNVS_BASE_ADDR);
+	u32 value;
+	value = readl(mx6_snvs_base + SNVS_LPCR);
+	/*set TOP and DP_EN bit*/
+	writel(value | 0x60, mx6_snvs_base + SNVS_LPCR);
+}
+
+#ifdef CONFIG_IMX_PCIE
+static const struct imx_pcie_platform_data mx6_hdmidongle_pcie_data __initconst = {
+	.pcie_pwr_en	= HDMIDONGLE_PCIE_PWR_EN,
+	.pcie_rst	= HDMIDONGLE_PCIE_RST,
+	.pcie_wake_up	= HDMIDONGLE_PCIE_WAKE,
+	.pcie_dis	= HDMIDONGLE_PCIE_DIS,
+};
+#endif
+
+/*!
+ * Board specific initialization.
+ */
+static void __init mx6_hdmidongle_board_init(void)
+{
+	int i;
+
+	if (cpu_is_mx6q()) {
+		if (board_is_mx6_revb() || board_is_mx6_revc())
+			mxc_iomux_v3_setup_multiple_pads(mx6q_hdmidongle_rev_b_pads,
+				ARRAY_SIZE(mx6q_hdmidongle_rev_b_pads));
+		else
+			mxc_iomux_v3_setup_multiple_pads(mx6q_hdmidongle_rev_a_pads,
+				ARRAY_SIZE(mx6q_hdmidongle_rev_a_pads));
+	} else if (cpu_is_mx6dl()) {
+		if (board_is_mx6_revb() || board_is_mx6_revc())
+			mxc_iomux_v3_setup_multiple_pads(mx6dl_hdmidongle_rev_b_pads,
+				ARRAY_SIZE(mx6dl_hdmidongle_rev_b_pads));
+		else
+			mxc_iomux_v3_setup_multiple_pads(mx6dl_hdmidongle_rev_a_pads,
+				ARRAY_SIZE(mx6dl_hdmidongle_rev_a_pads));
+	}
+
+	gp_reg_id = hdmidongle_dvfscore_data.reg_id;
+	soc_reg_id = hdmidongle_dvfscore_data.soc_id;
+	pu_reg_id = hdmidongle_dvfscore_data.pu_id;
+	mx6q_hdmidongle_init_uart();
+
+	/*
+	 * MX6DL/Solo only supports single IPU
+	 * The following codes are used to change ipu id
+	 * and display id information for MX6DL/Solo. Then
+	 * register 1 IPU device and up to 2 displays for
+	 * MX6DL/Solo
+	 */
+	if (cpu_is_mx6dl())
+		hdmi_core_data.disp_id = 0;
+
+	imx6q_add_mxc_hdmi_core(&hdmi_core_data);
+
+	imx6q_add_ipuv3(0, &ipu_data[0]);
+	if (cpu_is_mx6q())
+		imx6q_add_ipuv3(1, &ipu_data[1]);
+	for (i = 0; i < ARRAY_SIZE(hdmidongle_fb_data); i++)
+		imx6q_add_ipuv3fb(i, &hdmidongle_fb_data[i]);
+
+	imx6q_add_vdoa();
+
+	imx6q_add_v4l2_output(0);
+
+	imx6q_add_imx_snvs_rtc();
+
+	imx6q_add_imx_i2c(1, &mx6q_hdmidongle_i2c_data);
+    imx6q_add_imx_i2c(2, &mx6q_hdmidongle_i2c_data);
+
+	i2c_register_board_info(1, mxc_i2c1_board_info,
+			ARRAY_SIZE(mxc_i2c1_board_info));
+
+	mx6q_hdmidongle_init_wm8326();
+
+	imx6q_add_mxc_hdmi(&hdmi_data);
+
+	imx6q_add_anatop_thermal_imx(1, &mx6q_hdmidongle_anatop_thermal_data);
+	imx6q_add_pm_imx(0, &mx6q_hdmidongle_pm_data);
+	/* Move sd3 to first because sd3 connect to emmc.
+	   Mfgtools want emmc is mmcblk0 and other sd card is mmcblk1.
+	*/
+	if (board_is_mx6_revc())
+		imx6q_add_sdhci_usdhc_imx(2, &mx6q_hdmidongle_revc_sd3_data);
+	else
+		imx6q_add_sdhci_usdhc_imx(2, &mx6q_hdmidongle_sd3_data);
+	imx6q_add_sdhci_usdhc_imx(1, &mx6q_hdmidongle_sd2_data);
+	if (board_is_mx6_reva())
+		imx6q_add_sdhci_usdhc_imx(0, &mx6q_hdmidongle_sd1_data);
+	imx_add_viv_gpu(&imx6_gpu_data, &imx6q_gpu_pdata);
+	imx6q_hdmidongle_init_usb();
+
+	imx6q_add_vpu();
+
+	platform_device_register(&hdmidongle_vmmc_reg_devices);
+
+	imx6q_add_otp();
+	imx6q_add_viim();
+	imx6q_add_imx2_wdt(0, NULL);
+	imx6q_add_dma();
+	if (board_is_mx6_revb() || board_is_mx6_revc())
+		imx6q_add_gpmi(&mx6_gpmi_nand_platform_data);
+
+	imx6q_add_dvfs_core(&hdmidongle_dvfscore_data);
+	#ifndef CONFIG_MX6_INTER_LDO_BYPASS
+	mx6_cpu_regulator_init();
+	#endif
+
+	imx6q_add_ion(0, &imx_ion_data,
+		sizeof(imx_ion_data) + sizeof(struct ion_platform_heap));
+
+	imx6q_add_device_buttons();
+
+	imx6q_add_hdmi_soc();
+	imx6q_add_hdmi_soc_dai();
+
+	if (board_is_mx6_reva()) {
+		gpio_request(HDMIDONGLE_BT_RST, "bt_reset");
+		gpio_direction_output(HDMIDONGLE_BT_RST, 1);
+		gpio_set_value(HDMIDONGLE_BT_RST, 1);
+		mdelay(1000);
+		gpio_request(HDMIDONGLE_BT_EN, "bt_en");
+		gpio_direction_output(HDMIDONGLE_BT_EN, 1);
+		gpio_set_value(HDMIDONGLE_BT_EN, 1);
+
+		mdelay(1000);
+		gpio_request(HDMIDONGLE_WL_EN, "wl_en");
+		gpio_direction_output(HDMIDONGLE_WL_EN, 1);
+		gpio_set_value(HDMIDONGLE_WL_EN, 1);
+		mdelay(1000);
+#ifdef CONFIG_IMX_PCIE
+	} else if (board_is_mx6_revb() || board_is_mx6_revc()) {
+		/* Add PCIe RC interface support */
+		imx6q_add_pcie(&mx6_hdmidongle_pcie_data);
+		wake_lock_init(&pcie_wake_lock, WAKE_LOCK_SUSPEND, "pcie_workaround");
+		wake_lock(&pcie_wake_lock);
+#endif
+	}
+	pm_power_off = mx6_snvs_poweroff;
+	imx6q_add_busfreq();
+}
+
+extern void __iomem *twd_base;
+static void __init mx6_hdmidongle_timer_init(void)
+{
+	struct clk *uart_clk;
+#ifdef CONFIG_LOCAL_TIMERS
+	twd_base = ioremap(LOCAL_TWD_ADDR, SZ_256);
+	BUG_ON(!twd_base);
+#endif
+	mx6_clocks_init(32768, 24000000, 0, 0);
+
+	uart_clk = clk_get_sys("imx-uart.0", NULL);
+	early_console_setup(UART4_BASE_ADDR, uart_clk);
+}
+
+static struct sys_timer mx6_hdmidongle_timer = {
+	.init   = mx6_hdmidongle_timer_init,
+};
+
+static void __init mx6q_hdmidongle_reserve(void)
+{
+	phys_addr_t phys;
+	int i;
+
+#if defined(CONFIG_MXC_GPU_VIV) || defined(CONFIG_MXC_GPU_VIV_MODULE)
+	if (imx6q_gpu_pdata.reserved_mem_size) {
+		phys = memblock_alloc_base(imx6q_gpu_pdata.reserved_mem_size,
+					   SZ_4K, SZ_1G);
+		memblock_remove(phys, imx6q_gpu_pdata.reserved_mem_size);
+		imx6q_gpu_pdata.reserved_mem_base = phys;
+	}
+#endif
+#if defined(CONFIG_ION)
+	if (imx_ion_data.heaps[0].size) {
+		phys = memblock_alloc(imx_ion_data.heaps[0].size, SZ_4K);
+		memblock_remove(phys, imx_ion_data.heaps[0].size);
+		imx_ion_data.heaps[0].base = phys;
+	}
+#endif
+
+	for (i = 0; i < ARRAY_SIZE(hdmidongle_fb_data); i++)
+		if (hdmidongle_fb_data[i].res_size[0]) {
+			/* reserve for background buffer */
+			phys = memblock_alloc(hdmidongle_fb_data[i].res_size[0],
+						SZ_4K);
+			memblock_remove(phys, hdmidongle_fb_data[i].res_size[0]);
+			hdmidongle_fb_data[i].res_base[0] = phys;
+		}
+}
+
+/*
+ * initialize __mach_desc_MX6Q_HDMIDONGLE data structure.
+ */
+MACHINE_START(MX6Q_HDMIDONGLE, "Freescale i.MX 6Quad/DualLite HDMI Dongle Board")
+	/* Maintainer: Freescale Semiconductor, Inc. */
+	.boot_params = MX6_PHYS_OFFSET + 0x100,
+	.fixup = fixup_mxc_board,
+	.map_io = mx6_map_io,
+	.init_irq = mx6_init_irq,
+	.init_machine = mx6_hdmidongle_board_init,
+	.timer = &mx6_hdmidongle_timer,
+	.reserve = mx6q_hdmidongle_reserve,
+MACHINE_END
diff --git a/arch/arm/mach-mx6/board-mx6q_hdmidongle.h b/arch/arm/mach-mx6/board-mx6q_hdmidongle.h
new file mode 100644
index 000000000000..bf3a4b73db37
--- /dev/null
+++ b/arch/arm/mach-mx6/board-mx6q_hdmidongle.h
@@ -0,0 +1,337 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef _BOARD_MX6Q_HDMIDONGLE_H
+#define _BOARD_MX6Q_HDMIDONGLE_H
+#include <mach/iomux-mx6q.h>
+
+static iomux_v3_cfg_t mx6q_hdmidongle_rev_a_pads[] = {
+	/* SPI2 for PMIC communication port */
+	MX6Q_PAD_EIM_OE__ECSPI2_MISO,
+	MX6Q_PAD_EIM_RW__ECSPI2_SS0,
+	MX6Q_PAD_EIM_CS0__ECSPI2_SCLK,
+	MX6Q_PAD_EIM_CS1__ECSPI2_MOSI,
+
+	/*USB_OTG_DET(USB OTG cable plug detect) */
+	MX6Q_PAD_EIM_A16__GPIO_2_22,
+	/*BT_WAKEUP_HOST(Combo module BT wake-up output) */
+	MX6Q_PAD_EIM_A25__GPIO_5_2,
+	/* HOST_WAKEUP_BT(CPU wakeup BT signal)*/
+	MX6Q_PAD_EIM_D16__GPIO_3_16,
+
+	/* I2C3  */
+	MX6Q_PAD_EIM_D17__I2C3_SCL,
+	MX6Q_PAD_EIM_D18__I2C3_SDA,
+
+	/* USB OC pin */
+	MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC,
+	/* WLAN_WAKEUP_HOST(Combo module WLAN host wake-up output) */
+	MX6Q_PAD_EIM_D22__GPIO_3_22,
+
+	/* BT_UART2  */
+	MX6Q_PAD_EIM_D26__UART2_TXD,
+	MX6Q_PAD_EIM_D27__UART2_RXD,
+	MX6Q_PAD_EIM_D28__UART2_CTS,
+	MX6Q_PAD_EIM_D29__UART2_RTS,
+
+	/*BT_nRST(Combo module BT reset signal)*/
+	MX6Q_PAD_EIM_DA7__GPIO_3_7,
+
+	/*BT_REG_ON(Combo module BT Internal regulators power enable/disable)*/
+	MX6Q_PAD_EIM_DA9__GPIO_3_9,
+
+	/*WL_REG_ON(Combo module WLAN Internal regulators power enable/disable)*/
+	MX6Q_PAD_EIM_DA10__GPIO_3_10,
+
+	/* GPIO2 */
+	MX6Q_PAD_EIM_A22__GPIO_2_16,	/* Boot Mode Select */
+	MX6Q_PAD_EIM_A21__GPIO_2_17,	/* Boot Mode Select */
+	MX6Q_PAD_EIM_A20__GPIO_2_18,	/* Boot Mode Select */
+	MX6Q_PAD_EIM_A19__GPIO_2_19,	/* Boot Mode Select */
+	MX6Q_PAD_EIM_A18__GPIO_2_20,	/* Boot Mode Select */
+	MX6Q_PAD_EIM_A17__GPIO_2_21,	/* Boot Mode Select */
+	MX6Q_PAD_EIM_RW__GPIO_2_26,		/* Boot Mode Select */
+	MX6Q_PAD_EIM_LBA__GPIO_2_27,	/* Boot Mode Select */
+	MX6Q_PAD_EIM_EB0__GPIO_2_28,	/* Boot Mode Select */
+	MX6Q_PAD_EIM_EB1__GPIO_2_29,	/* Boot Mode Select */
+	MX6Q_PAD_EIM_EB2__GPIO_2_30,	/* Boot Mode Select */
+	MX6Q_PAD_EIM_EB3__GPIO_2_31,	/* Boot Mode Select */
+
+	/* GPIO3 */
+	MX6Q_PAD_EIM_DA0__GPIO_3_0,	/*  Boot Mode Select */
+	MX6Q_PAD_EIM_DA1__GPIO_3_1,	/*  Boot Mode Select */
+	MX6Q_PAD_EIM_DA2__GPIO_3_2,	/*  Boot Mode Select */
+	MX6Q_PAD_EIM_DA3__GPIO_3_3,	/*  Boot Mode Select */
+	MX6Q_PAD_EIM_DA4__GPIO_3_4,	/*  Boot Mode Select */
+	MX6Q_PAD_EIM_DA5__GPIO_3_5,	/*  Boot Mode Select */
+	MX6Q_PAD_EIM_DA6__GPIO_3_6,	/*  Boot Mode Select */
+	MX6Q_PAD_EIM_DA8__GPIO_3_8,	/*  Boot Mode Select */
+	MX6Q_PAD_EIM_DA11__GPIO_3_11,	/*  Boot Mode Select */
+	MX6Q_PAD_EIM_DA12__GPIO_3_12,	/*  Boot Mode Select */
+	MX6Q_PAD_EIM_DA13__GPIO_3_13,	/*  Boot Mode Select */
+	MX6Q_PAD_EIM_DA14__GPIO_3_14,	/*  Boot Mode Select */
+	MX6Q_PAD_EIM_DA15__GPIO_3_15,	/*  Boot Mode Select */
+
+	/* GPIO5 */
+	MX6Q_PAD_EIM_WAIT__GPIO_5_0,	/* Boot Mode Select */
+	MX6Q_PAD_EIM_A24__GPIO_5_4,	/* Boot Mode Select */
+
+	/* GPIO6 */
+	MX6Q_PAD_EIM_A23__GPIO_6_6,	/* Boot Mode Select */
+
+	/* I2C1  */
+	MX6Q_PAD_CSI0_DAT8__I2C1_SDA,
+	MX6Q_PAD_CSI0_DAT9__I2C1_SCL,
+
+	/* UART1 for debug */
+	MX6Q_PAD_CSI0_DAT10__UART1_TXD,
+	MX6Q_PAD_CSI0_DAT11__UART1_RXD,
+
+	/* SD1 (Combo module WLAN SDIO )*/
+	MX6Q_PAD_SD1_CLK__USDHC1_CLK,
+	MX6Q_PAD_SD1_CMD__USDHC1_CMD,
+	MX6Q_PAD_SD1_DAT0__USDHC1_DAT0,
+	MX6Q_PAD_SD1_DAT1__USDHC1_DAT1,
+	MX6Q_PAD_SD1_DAT2__USDHC1_DAT2,
+	MX6Q_PAD_SD1_DAT3__USDHC1_DAT3,
+
+	/* SD2 (MicroSD SDIO CMD)*/
+	MX6Q_PAD_SD2_CLK__USDHC2_CLK,
+	MX6Q_PAD_SD2_CMD__USDHC2_CMD,
+	MX6Q_PAD_SD2_DAT0__USDHC2_DAT0,
+	MX6Q_PAD_SD2_DAT1__USDHC2_DAT1,
+	MX6Q_PAD_SD2_DAT2__USDHC2_DAT2,
+	MX6Q_PAD_SD2_DAT3__USDHC2_DAT3,
+	/*SD_DET (SD plug-in detect interrupt)*/
+	MX6Q_PAD_GPIO_4__GPIO_1_4,
+
+	/* SD3 (eMMC SDIO)*/
+	MX6Q_PAD_SD3_CLK__USDHC3_CLK_50MHZ,
+	MX6Q_PAD_SD3_CMD__USDHC3_CMD_50MHZ,
+	MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ,
+	MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ,
+	MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ,
+	MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ,
+	MX6Q_PAD_SD3_DAT4__USDHC3_DAT4_50MHZ,
+	MX6Q_PAD_SD3_DAT5__USDHC3_DAT5_50MHZ,
+	MX6Q_PAD_SD3_DAT6__USDHC3_DAT6_50MHZ,
+	MX6Q_PAD_SD3_DAT7__USDHC3_DAT7_50MHZ,
+	MX6Q_PAD_SD3_RST__USDHC3_RST,
+
+	/* UART4 for debug */
+	MX6Q_PAD_KEY_COL0__UART4_TXD,
+	MX6Q_PAD_KEY_ROW0__UART4_RXD,
+
+	/* I2C2 */
+	MX6Q_PAD_KEY_COL3__I2C2_SCL,	/* GPIO4[12] */
+	MX6Q_PAD_KEY_ROW3__I2C2_SDA,	/* GPIO4[13] */
+
+	/*DCDC5V_PWREN(5V DCDC BOOST control signal)*/
+	MX6Q_PAD_KEY_COL4__GPIO_4_14,
+
+	/*USB_OTG_PWREN(USB OTG power change control signal)*/
+	MX6Q_PAD_KEY_ROW4__GPIO_4_15,
+
+	/* USBOTG ID pin */
+	MX6Q_PAD_GPIO_1__USBOTG_ID,
+
+	/* I2C3 */
+	MX6Q_PAD_GPIO_5__I2C3_SCL,
+	MX6Q_PAD_GPIO_16__I2C3_SDA,
+
+	/*WDOG(Watch dog output)*/
+	MX6Q_PAD_GPIO_9__GPIO_1_9,
+
+	/*PMIC_nINT(PMIC interrupt signal)*/
+	MX6Q_PAD_NANDF_CS0__GPIO_6_11,
+
+	/*GPIO_nRST(GPIO shutdown control)*/
+	MX6Q_PAD_NANDF_CS1__GPIO_6_14,
+
+	/*PWRKEY_DET(Power key press detection)*/
+	MX6Q_PAD_NANDF_CS3__GPIO_6_16,
+
+	/*CHG_SYS_ON(Charger auto power on control signal)*/
+	MX6Q_PAD_NANDF_D6__GPIO_2_6,
+
+	/*IR_RC*/
+	MX6Q_PAD_SD4_DAT6__GPIO_2_14,
+};
+
+static iomux_v3_cfg_t mx6q_hdmidongle_rev_b_pads[] = {
+	/* SPI2 for PMIC communication port */
+	MX6Q_PAD_EIM_OE__ECSPI2_MISO,
+	MX6Q_PAD_EIM_RW__ECSPI2_SS0,
+	MX6Q_PAD_EIM_CS0__ECSPI2_SCLK,
+	MX6Q_PAD_EIM_CS1__ECSPI2_MOSI,
+
+	/*USB_OTG_DET(USB OTG cable plug detect) */
+	MX6Q_PAD_EIM_A16__GPIO_2_22,
+	/*WLAN_CLKREQn*/
+	MX6Q_PAD_EIM_A25__GPIO_5_2,
+
+	/* WLAN_ACT */
+	MX6Q_PAD_EIM_D17__GPIO_3_17,
+
+	/*BT_PERI*/
+	MX6Q_PAD_EIM_D18__GPIO_3_18,
+
+	/* USB OC pin */
+	MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC,
+
+	/* WLAN_WAKEn (PM event, OD, used to reactivate the PCIe main PWR and REF CLK) */
+	MX6Q_PAD_EIM_D22__GPIO_3_22,
+
+
+	/*WLAN_PERSTn (PCIe rst signal, avtive LOW)*/
+	MX6Q_PAD_EIM_DA9__GPIO_3_9,
+
+	/*WLAN_PDn (Externally shutdown RTL8192)*/
+	MX6Q_PAD_EIM_DA10__GPIO_3_10,
+
+	/* GPIO2 */
+	MX6Q_PAD_EIM_A22__GPIO_2_16,	/* Boot Mode Select */
+	MX6Q_PAD_EIM_A21__GPIO_2_17,	/* Boot Mode Select */
+	MX6Q_PAD_EIM_A20__GPIO_2_18,	/* Boot Mode Select */
+	MX6Q_PAD_EIM_A19__GPIO_2_19,	/* Boot Mode Select */
+	MX6Q_PAD_EIM_A18__GPIO_2_20,	/* Boot Mode Select */
+	MX6Q_PAD_EIM_A17__GPIO_2_21,	/* Boot Mode Select */
+	MX6Q_PAD_EIM_RW__GPIO_2_26,		/* Boot Mode Select */
+	MX6Q_PAD_EIM_LBA__GPIO_2_27,	/* Boot Mode Select */
+	MX6Q_PAD_EIM_EB0__GPIO_2_28,	/* Boot Mode Select */
+	MX6Q_PAD_EIM_EB1__GPIO_2_29,	/* Boot Mode Select */
+	MX6Q_PAD_EIM_EB2__GPIO_2_30,	/* Boot Mode Select */
+	MX6Q_PAD_EIM_EB3__GPIO_2_31,	/* Boot Mode Select */
+
+	/* GPIO3 */
+	MX6Q_PAD_EIM_DA0__GPIO_3_0,	/*  Boot Mode Select */
+	MX6Q_PAD_EIM_DA1__GPIO_3_1,	/*  Boot Mode Select */
+	MX6Q_PAD_EIM_DA2__GPIO_3_2,	/*  Boot Mode Select */
+	MX6Q_PAD_EIM_DA3__GPIO_3_3,	/*  Boot Mode Select */
+	MX6Q_PAD_EIM_DA4__GPIO_3_4,	/*  Boot Mode Select */
+	MX6Q_PAD_EIM_DA5__GPIO_3_5,	/*  Boot Mode Select */
+	MX6Q_PAD_EIM_DA6__GPIO_3_6,	/*  Boot Mode Select */
+	MX6Q_PAD_EIM_DA8__GPIO_3_8,	/*  Boot Mode Select */
+	MX6Q_PAD_EIM_DA11__GPIO_3_11,	/*  Boot Mode Select */
+	MX6Q_PAD_EIM_DA12__GPIO_3_12,	/*  Boot Mode Select */
+	MX6Q_PAD_EIM_DA13__GPIO_3_13,	/*  Boot Mode Select */
+	MX6Q_PAD_EIM_DA14__GPIO_3_14,	/*  Boot Mode Select */
+	MX6Q_PAD_EIM_DA15__GPIO_3_15,	/*  Boot Mode Select */
+
+	/* GPIO5 */
+	MX6Q_PAD_EIM_WAIT__GPIO_5_0,	/* Boot Mode Select */
+	MX6Q_PAD_EIM_A24__GPIO_5_4,		/* Boot Mode Select */
+
+	/* GPIO6 */
+	MX6Q_PAD_EIM_A23__GPIO_6_6,	/* Boot Mode Select */
+
+
+	/* SD2 (MicroSD SDIO CMD)*/
+	MX6Q_PAD_SD2_CLK__USDHC2_CLK,
+	MX6Q_PAD_SD2_CMD__USDHC2_CMD,
+	MX6Q_PAD_SD2_DAT0__USDHC2_DAT0,
+	MX6Q_PAD_SD2_DAT1__USDHC2_DAT1,
+	MX6Q_PAD_SD2_DAT2__USDHC2_DAT2,
+	MX6Q_PAD_SD2_DAT3__USDHC2_DAT3,
+	/*SD_DET (SD plug-in detect interrupt)*/
+	MX6Q_PAD_GPIO_4__GPIO_1_4,
+
+	/* SD3 (eMMC SDIO)*/
+	MX6Q_PAD_SD3_CLK__USDHC3_CLK_50MHZ,
+	MX6Q_PAD_SD3_CMD__USDHC3_CMD_50MHZ,
+	MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ,
+	MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ,
+	MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ,
+	MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ,
+	MX6Q_PAD_SD3_DAT4__USDHC3_DAT4_50MHZ,
+	MX6Q_PAD_SD3_DAT5__USDHC3_DAT5_50MHZ,
+	MX6Q_PAD_SD3_DAT6__USDHC3_DAT6_50MHZ,
+	MX6Q_PAD_SD3_DAT7__USDHC3_DAT7_50MHZ,
+	MX6Q_PAD_SD3_RST__USDHC3_RST,
+
+	/* UART4 for debug */
+	MX6Q_PAD_KEY_COL0__UART4_TXD,
+	MX6Q_PAD_KEY_ROW0__UART4_RXD,
+
+	/*SD2_VSELECT (SD2 SDXC power exchange control signal)*/
+	MX6Q_PAD_KEY_ROW1__GPIO_4_9,
+
+	/*PWRKEY_DET (Pwr button detection interrupt)*/
+	MX6Q_PAD_ENET_RXD0__GPIO_1_27,
+
+	/*USB_OTG_PWREN(USB OTG power change control signal)*/
+	MX6Q_PAD_KEY_ROW4__GPIO_4_15,
+
+	/* USBOTG ID pin */
+	MX6Q_PAD_GPIO_1__USBOTG_ID,
+
+	/* I2C2 */
+	MX6Q_PAD_KEY_COL3__I2C2_SCL,	/* GPIO4[12] */
+	MX6Q_PAD_KEY_ROW3__I2C2_SDA,	/* GPIO4[13] */
+
+	/* I2C3 */
+	MX6Q_PAD_GPIO_5__I2C3_SCL,
+	MX6Q_PAD_GPIO_16__I2C3_SDA,
+
+	/*WDOG(Watch dog output)*/
+	MX6Q_PAD_GPIO_9__GPIO_1_9,
+
+	/*PMIC_nINT(PMIC interrupt signal)*/
+	MX6Q_PAD_SD4_DAT3__GPIO_2_11,
+
+	/*GPIO_nRST(GPIO shutdown control)*/
+	MX6Q_PAD_SD4_DAT1__GPIO_2_9,
+
+	/*CHG_SYS_ON(Charger auto power on control signal)*/
+	MX6Q_PAD_SD4_DAT6__GPIO_2_14,
+};
+
+/* The GPMI is conflicted with SD3, so init this in the driver. */
+static iomux_v3_cfg_t mx6q_gpmi_nand[] __initdata = {
+	MX6Q_PAD_NANDF_CLE__RAWNAND_CLE,
+	MX6Q_PAD_NANDF_ALE__RAWNAND_ALE,
+	MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N,
+	MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N,
+	MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N,
+	MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N,
+	MX6Q_PAD_NANDF_RB0__RAWNAND_READY0,
+	MX6Q_PAD_SD4_DAT0__RAWNAND_DQS,
+	MX6Q_PAD_NANDF_D0__RAWNAND_D0,
+	MX6Q_PAD_NANDF_D1__RAWNAND_D1,
+	MX6Q_PAD_NANDF_D2__RAWNAND_D2,
+	MX6Q_PAD_NANDF_D3__RAWNAND_D3,
+	MX6Q_PAD_NANDF_D4__RAWNAND_D4,
+	MX6Q_PAD_NANDF_D5__RAWNAND_D5,
+	MX6Q_PAD_NANDF_D6__RAWNAND_D6,
+	MX6Q_PAD_NANDF_D7__RAWNAND_D7,
+	MX6Q_PAD_SD4_CMD__RAWNAND_RDN,
+	MX6Q_PAD_SD4_CLK__RAWNAND_WRN,
+	MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN,
+};
+
+static iomux_v3_cfg_t mx6q_hdmidongle_hdmi_ddc_pads[] = {
+	MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL, /* HDMI DDC SCL */
+	MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA, /* HDMI DDC SDA */
+};
+
+static iomux_v3_cfg_t mx6q_hdmidongle_i2c2_pads[] = {
+	MX6Q_PAD_KEY_COL3__I2C2_SCL,	/* I2C2 SCL */
+	MX6Q_PAD_KEY_ROW3__I2C2_SDA,	/* I2C2 SDA */
+};
+
+#endif
diff --git a/arch/arm/mach-mx6/mx6q_hdmidongle_pmic_wm831x.c b/arch/arm/mach-mx6/mx6q_hdmidongle_pmic_wm831x.c
new file mode 100644
index 000000000000..aa28a198d9d9
--- /dev/null
+++ b/arch/arm/mach-mx6/mx6q_hdmidongle_pmic_wm831x.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/regulator/machine.h>
+#include <linux/io.h>
+
+#ifdef CONFIG_MFD_WM831X
+#include <linux/mfd/wm831x/core.h>
+#include <linux/mfd/wm831x/pdata.h>
+#include <linux/mfd/wm831x/regulator.h>
+#include <linux/mfd/wm831x/gpio.h>
+
+#if 0
+/* 1.4125, 1.4125. 1.5 */
+#define WM831X_DC1_ON_CONFIG_VAL            (0x48<<WM831X_DC1_ON_VSEL_SHIFT)
+#define WM831X_DC2_ON_CONFIG_VAL            (0x48<<WM831X_DC2_ON_VSEL_SHIFT)
+#define WM831X_DC3_ON_CONFIG_VAL            (0x1A<<WM831X_DC3_ON_VSEL_SHIFT)
+#else
+/* 1.375, 1.375. 1.5 */
+
+#define WM831X_DC1_ON_CONFIG_VAL            (0x44<<WM831X_DC1_ON_VSEL_SHIFT)
+#define WM831X_DC2_ON_CONFIG_VAL            (0x44<<WM831X_DC2_ON_VSEL_SHIFT)
+#define WM831X_DC3_ON_CONFIG_VAL            (0x1A<<WM831X_DC3_ON_VSEL_SHIFT)
+
+#endif
+
+#define WM831X_DC1_DVS_MODE_VAL	(0x02<<WM831X_DC1_DVS_SRC_SHIFT)
+#define WM831X_DC2_DVS_MODE_VAL	(0x02<<WM831X_DC2_DVS_SRC_SHIFT)
+
+#define WM831X_DC1_DVS_CONTROL_VAL	(0x20<<WM831X_DC1_DVS_VSEL_SHIFT)
+#define WM831X_DC2_DVS_CONTROL_VAL	(0x20<<WM831X_DC2_DVS_VSEL_SHIFT)
+
+#define WM831X_DC1_DVS_MASK	(WM831X_DC1_DVS_SRC_MASK|WM831X_DC1_DVS_VSEL_MASK)
+#define WM831X_DC2_DVS_MASK	(WM831X_DC2_DVS_SRC_MASK|WM831X_DC1_DVS_VSEL_MASK)
+
+#define WM831X_DC1_DVS_VAL	(WM831X_DC1_DVS_MODE_VAL|WM831X_DC1_DVS_CONTROL_VAL)
+#define WM831X_DC2_DVS_VAL                   (WM831X_DC2_DVS_MODE_VAL|WM831X_DC2_DVS_CONTROL_VAL)
+
+#define WM831X_GPN_FN_VAL_HW_EN	(0x0A<<WM831X_GPN_FN_SHIFT)
+#define WM831X_GPN_FN_VAL_HW_CTL	(0x0C<<WM831X_GPN_FN_SHIFT)
+#define WM831X_GPN_FN_VAL_DVS1	(0x08<<WM831X_GPN_FN_SHIFT)
+
+#define WM831X_GPN_DIR_VAL	(0x1<<WM831X_GPN_DIR_SHIFT)
+#define WM831X_GPN_PULL_VAL	(0x3<<WM831X_GPN_PULL_SHIFT)
+#define WM831X_GPN_INT_MODE_VAL	(0x1<<WM831X_GPN_INT_MODE_SHIFT)
+#define WM831X_GPN_POL_VAL	(0x1<<WM831X_GPN_POL_SHIFT)
+#define WM831X_GPN_ENA_VAL	(0x1<<WM831X_GPN_ENA_SHIFT)
+
+#define WM831X_GPIO7_8_9_MASK	(WM831X_GPN_DIR_MASK|WM831X_GPN_INT_MODE_MASK| \
+						WM831X_GPN_PULL_MASK|WM831X_GPN_POL_MASK|WM831X_GPN_FN_MASK)
+
+
+#define WM831X_GPIO7_VAL	(WM831X_GPN_DIR_VAL|WM831X_GPN_PULL_VAL|WM831X_GPN_INT_MODE_VAL| \
+						WM831X_GPN_POL_VAL|WM831X_GPN_ENA_VAL|WM831X_GPN_FN_VAL_HW_EN)
+#define WM831X_GPIO8_VAL	(WM831X_GPN_DIR_VAL|WM831X_GPN_PULL_VAL|WM831X_GPN_INT_MODE_VAL| \
+						WM831X_GPN_POL_VAL|WM831X_GPN_ENA_VAL|WM831X_GPN_FN_VAL_HW_CTL)
+#define WM831X_GPIO9_VAL	(WM831X_GPN_DIR_VAL|WM831X_GPN_PULL_VAL|WM831X_GPN_INT_MODE_VAL| \
+						WM831X_GPN_POL_VAL|WM831X_GPN_ENA_VAL|WM831X_GPN_FN_VAL_DVS1)
+
+#define WM831X_STATUS_LED_MASK                0xC000
+#define WM831X_STATUS_LED_ON                  (0x1 << 14)
+#define WM831X_STATUS_LED_OFF                 (0x0 << 14)
+
+static int wm8326_post_init(struct wm831x *wm831x)
+{
+	wm831x_set_bits(wm831x, WM831X_DC1_ON_CONFIG, WM831X_DC1_ON_VSEL_MASK, WM831X_DC1_ON_CONFIG_VAL);
+	wm831x_set_bits(wm831x, WM831X_DC2_ON_CONFIG, WM831X_DC2_ON_VSEL_MASK, WM831X_DC2_ON_CONFIG_VAL);
+	wm831x_set_bits(wm831x, WM831X_DC3_ON_CONFIG, WM831X_DC3_ON_VSEL_MASK, WM831X_DC3_ON_CONFIG_VAL);
+
+	wm831x_set_bits(wm831x, WM831X_DC1_DVS_CONTROL, WM831X_DC1_DVS_MASK, WM831X_DC1_DVS_VAL);
+	wm831x_set_bits(wm831x, WM831X_DC2_DVS_CONTROL, WM831X_DC2_DVS_MASK, WM831X_DC2_DVS_VAL);
+
+	wm831x_set_bits(wm831x, WM831X_GPIO7_CONTROL, WM831X_GPIO7_8_9_MASK, WM831X_GPIO7_VAL);
+	wm831x_set_bits(wm831x, WM831X_GPIO8_CONTROL, WM831X_GPIO7_8_9_MASK, WM831X_GPIO8_VAL);
+	wm831x_set_bits(wm831x, WM831X_GPIO9_CONTROL, WM831X_GPIO7_8_9_MASK, WM831X_GPIO9_VAL);
+
+	wm831x_set_bits(wm831x, WM831X_STATUS_LED_1 , WM831X_STATUS_LED_MASK, WM831X_STATUS_LED_OFF);
+	wm831x_set_bits(wm831x, WM831X_STATUS_LED_2 , WM831X_STATUS_LED_MASK, WM831X_STATUS_LED_ON);
+	return 0;
+}
+
+static struct wm831x_pdata hdmidongle_wm8326_pdata = {
+	.post_init = wm8326_post_init,
+};
+
+static struct i2c_board_info mxc_i2c2_board_info[] __initdata = {
+	{
+	I2C_BOARD_INFO("wm8326", 0x34),
+	.platform_data = &hdmidongle_wm8326_pdata,
+	},
+};
+
+int __init mx6q_hdmidongle_init_wm8326(void)
+{
+	return i2c_register_board_info(2, mxc_i2c2_board_info,
+			ARRAY_SIZE(mxc_i2c2_board_info));
+}
+#else
+int __init mx6q_hdmidongle_init_wm8326(void) {};
+#endif
+
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 054cdfe21298..4bb096d65c32 100755
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -98,5 +98,6 @@ extern void early_console_setup(unsigned long base, struct clk *clk);
 extern void mx6_cpu_regulator_init(void);
 extern int mx6q_sabreauto_init_pfuze100(u32 int_gpio);
 extern int mx6q_sabresd_init_pfuze100(u32 int_gpio);
+extern int mx6q_hdmidongle_init_wm8326(void);
 extern void imx_print_silicon_rev(const char *cpu, int srev);
 #endif
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 88210d976378..f6b5c0efc3e8 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -1118,5 +1118,6 @@ mx6q_sabrelite		MACH_MX6Q_SABRELITE	MX6Q_SABRELITE		3769
 mx6q_sabresd		MACH_MX6Q_SABRESD	MX6Q_SABRESD		3980
 mx6q_arm2		MACH_MX6Q_ARM2		MX6Q_ARM2		3837
 mx6sl_arm2		MACH_MX6SL_ARM2		MX6SL_ARM2		4091
+mx6q_hdmidongle		MACH_MX6Q_HDMIDONGLE    MX6Q_HDMIDONGLE		4284
 mx6sl_evk		MACH_MX6SL_EVK		MX6SL_EVK		4307