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authorArjan van de Ven <arjan@linux.intel.com>2006-12-17 21:49:57 +0100
committerAdrian Bunk <bunk@stusta.de>2006-12-17 21:49:57 +0100
commit5871db7738d0e2152c5ed35cef10029f2f26e05f (patch)
treece1cefb827bae9f19661d02c7ae09423ce57a9b4 /arch
parent862c29977ccf45acc4dcbad952deef30d4013141 (diff)
x86-64: Mark rdtsc as sync only for netburst, not for core2
On the Core2 cpus, the rdtsc instruction is not serializing (as defined in the architecture reference since rdtsc exists) and due to the deep speculation of these cores, it's possible that you can observe time go backwards between cores due to this speculation. Since the kernel already deals with this with the SYNC_RDTSC flag, the solution is simple, only assume that the instruction is serializing on family 15... The price one pays for this is a slightly slower gettimeofday (by a dozen or two cycles), but that increase is quite small to pay for a really-going-forward tsc counter. Backport by Chris Wright. Signed-off-by: Arjan van de Ven <arjan@linux.intel.com> Signed-off-by: Chris Wright <chrisw@sous-sol.org> Signed-off-by: Adrian Bunk <bunk@stusta.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/x86_64/kernel/setup.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/x86_64/kernel/setup.c b/arch/x86_64/kernel/setup.c
index a4a0bb5fb481..babbbaf823ea 100644
--- a/arch/x86_64/kernel/setup.c
+++ b/arch/x86_64/kernel/setup.c
@@ -1050,7 +1050,10 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
(c->x86 == 0x6 && c->x86_model >= 0x0e))
set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
- set_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
+ if (c->x86 == 15)
+ set_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
+ else
+ clear_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
c->x86_max_cores = intel_num_cpu_cores(c);
srat_detect_node();