diff options
| author | Bai Ping <b51503@freescale.com> | 2015-01-29 19:09:39 +0800 |
|---|---|---|
| committer | Bai Ping <b51503@freescale.com> | 2015-01-30 01:49:48 +0800 |
| commit | e2f17323916eae636e63353d742c986227b72702 (patch) | |
| tree | d88c8ddc0bb6856f31aa3be18794c9b4edb8c785 /arch | |
| parent | 912c6268b685a9aa158cb84f9c46c8e6176572a7 (diff) | |
MLK-10175 arm: imx6: Skip gating QSPI2 clk when M4 is enabled
When the M4 core is enabled on i.MX6, the QSPI2 clk can't be gated,
otherwise, the M4 will hang. This patch add a check to make sure when
M4 is enabled, just skip the QSPI2 clk gating operations.
Signed-off-by: Bai Ping <b51503@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-imx/clk-imx6sx.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/arch/arm/mach-imx/clk-imx6sx.c b/arch/arm/mach-imx/clk-imx6sx.c index 06dfe9bdd4bf..f64bf9a7b7ec 100644 --- a/arch/arm/mach-imx/clk-imx6sx.c +++ b/arch/arm/mach-imx/clk-imx6sx.c @@ -568,9 +568,10 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) * different gate, need explicitely gate the QSPI2 & GPMI_IO * during the clock init phase according to the SOC design. */ - writel_relaxed(readl_relaxed(base + 0x78) & ~(3 << CCM_CCGR_OFFSET(5)), base + 0x78); - writel_relaxed(readl_relaxed(base + 0x78) & ~(3 << CCM_CCGR_OFFSET(14)), base + 0x78); - + if (!imx_src_is_m4_enabled()) { + writel_relaxed(readl_relaxed(base + 0x78) & ~(3 << CCM_CCGR_OFFSET(5)), base + 0x78); + writel_relaxed(readl_relaxed(base + 0x78) & ~(3 << CCM_CCGR_OFFSET(14)), base + 0x78); + } clk_data.clks = clks; clk_data.clk_num = ARRAY_SIZE(clks); of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); |