imx6: phyFLEX: add support for PCM-958 module

Add support for the phytec WLAN module.

2 files changed, 97 insertions, 18 deletions

diff --git a/arch/arm/mach-mx6/board-mx6q_phyflex.h b/arch/arm/mach-mx6/board-mx6q_phyflex.h
index e98733a14574..fc823e577ba9 100644
--- a/arch/arm/mach-mx6/board-mx6q_phyflex.h
+++ b/arch/arm/mach-mx6/board-mx6q_phyflex.h
@@ -63,10 +63,6 @@ static iomux_v3_cfg_t mx6q_phytec_common_pads[] = {
 	MX6Q_PAD_ENET_TX_EN__ENET_TX_EN,
 	MX6Q_PAD_ENET_RXD1__MLB_MLBSIG,
 	MX6Q_PAD_ENET_TXD0__GPIO_1_30,
-	MX6Q_PAD_ENET_TXD1__MLB_MLBCLK,
-//MX6Q_PAD_ENET_RXD1__ENET_RDATA_1,
-//MX6Q_PAD_ENET_TXD1__ENET_TDATA_1,
-//MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC,
 	MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC,
 	MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0,
 	MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1,
@@ -107,10 +103,6 @@ static iomux_v3_cfg_t mx6q_phytec_common_pads[] = {
 	MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ,
 	MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ,
 	MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ,
-	MX6Q_PAD_SD3_DAT4__USDHC3_DAT4_50MHZ,
-	MX6Q_PAD_SD3_DAT5__USDHC3_DAT5_50MHZ,
-	MX6Q_PAD_SD3_DAT6__USDHC3_DAT6_50MHZ,
-	MX6Q_PAD_SD3_DAT7__USDHC3_DAT7_50MHZ,
 	MX6Q_PAD_SD3_RST__GPIO_7_8,
 	/* SD3_CD and SD3_WP */
 	MX6Q_PAD_ENET_RXD0__GPIO_1_27,
@@ -261,10 +253,6 @@ static iomux_v3_cfg_t mx6q_phytec_common_pads[] = {
 	MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_200MHZ,
 	MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_200MHZ,
 	MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_200MHZ,
-	MX6Q_PAD_SD3_DAT4__USDHC3_DAT4_200MHZ,
-	MX6Q_PAD_SD3_DAT5__USDHC3_DAT5_200MHZ,
-	MX6Q_PAD_SD3_DAT6__USDHC3_DAT6_200MHZ,
-	MX6Q_PAD_SD3_DAT7__USDHC3_DAT7_200MHZ,
 
 	MX6Q_PAD_SD2_CLK__USDHC2_CLK_200MHZ,
 	MX6Q_PAD_SD2_CMD__USDHC2_CMD_200MHZ,
@@ -272,6 +260,13 @@ static iomux_v3_cfg_t mx6q_phytec_common_pads[] = {
 	MX6Q_PAD_SD2_DAT1__USDHC2_DAT1_200MHZ,
 	MX6Q_PAD_SD2_DAT2__USDHC2_DAT2_200MHZ,
 	MX6Q_PAD_SD2_DAT3__USDHC2_DAT3_200MHZ,
+
+#if defined(CONFIG_WL12XX)
+	/* WL12xx IRQ/ENABLE */
+	MX6Q_PAD_SD3_DAT6__GPIO_6_18,
+	MX6Q_PAD_SD3_DAT7__GPIO_6_17,
+#endif
+
 };
 
 /* This iomux array is for phyFLEX-i.MX6 modules Rev. 1 */
diff --git a/arch/arm/mach-mx6/board-mx6q_phytec-sd.c b/arch/arm/mach-mx6/board-mx6q_phytec-sd.c
index c963048fd3cd..45ccf887a505 100644
--- a/arch/arm/mach-mx6/board-mx6q_phytec-sd.c
+++ b/arch/arm/mach-mx6/board-mx6q_phytec-sd.c
@@ -27,6 +27,21 @@
 #include "cpu_op-mx6.h"
 #include "board-mx6q_phytec-sd.h"
 
+#if defined(CONFIG_WL12XX)
+	#include <linux/delay.h>
+	#include <linux/wl12xx.h>
+	#include <linux/gpio.h>
+
+	#include <linux/regulator/anatop-regulator.h>
+	#include <linux/regulator/consumer.h>
+	#include <linux/regulator/machine.h>
+	#include <linux/regulator/fixed.h>
+
+	#define WLAN_IRQ	IMX_GPIO_NR(6, 17)
+	#define WLAN_ENABLE	IMX_GPIO_NR(6, 18)
+#endif
+
+
 static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(3, 50);
 static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(3, 100);
 static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(3, 200);
@@ -154,26 +169,83 @@ static int plt_sd3_pad_change(unsigned int index, int clock)
 
 #if defined(CONFIG_MACH_MX6Q_PHYFLEX)
 static struct esdhc_platform_data mx6_phytec_sd2_data __initconst = {
-//	.cd_gpio		= 0,
-//	.wp_gpio		= 0,
 	.support_18v		= 0,
-	.support_8bit		= 1,
+	.support_8bit		= 0,
 	.keep_power_at_suspend	= 1,
 	.delay_line		= 0,
 	.platform_pad_change	= plt_sd2_pad_change,
 };
 #endif
 
+#if !defined(CONFIG_WL12XX)
 static struct esdhc_platform_data mx6_phytec_sd3_data __initconst = {
-//	.cd_gpio		= 0,
-//	.wp_gpio		= 0,
 	.support_18v		= 0,
-	.support_8bit		= 1,
+	.support_8bit		= 0,
 	.keep_power_at_suspend	= 1,
 	.delay_line		= 0,
 	.platform_pad_change	= plt_sd3_pad_change,
 };
 
+#else
+static struct esdhc_platform_data mx6_phytec_sd3_data __initconst = {
+	.always_present		= 1,
+	.cd_gpio		= -1,
+	.wp_gpio		= -1,
+	.support_18v		= 0,
+	.support_8bit		= 0,
+	.keep_power_at_suspend	= 0,
+	.caps			= MMC_CAP_POWER_OFF_CARD,
+	.platform_pad_change	= plt_sd3_pad_change,
+};
+
+static void wl1271_set_power(bool enable)
+{
+	if (0 == enable) {
+		gpio_set_value(WLAN_ENABLE, 0);     /* momentarily disable */
+		mdelay(2);
+		gpio_set_value(WLAN_ENABLE, 1);
+	}
+}
+
+struct wl12xx_platform_data n6q_wlan_data __initdata = {
+	.irq		= gpio_to_irq(WLAN_IRQ),
+	.board_ref_clock = WL12XX_REFCLOCK_38, /* 38.4 MHz */
+	.set_power	= wl1271_set_power,
+};
+
+static struct regulator_consumer_supply n6q_vwl1271_consumers[] = {
+	REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.1"),
+};
+
+static struct regulator_init_data n6q_vwl1271_init = {
+	.constraints = {
+		.name		= "VDD_1.8V",
+		.valid_ops_mask	= REGULATOR_CHANGE_STATUS,
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(n6q_vwl1271_consumers),
+	.consumer_supplies	= n6q_vwl1271_consumers,
+};
+
+static struct fixed_voltage_config n6q_vwl1271_reg_config = {
+	.supply_name	= "vwl1271",
+	.microvolts	= 1800000, /* 1.80V */
+	.gpio		= -1,
+	.startup_delay	= 70000, /* 70ms */
+	.enable_high	= 1,
+	.enabled_at_boot = 0,
+	.init_data	= &n6q_vwl1271_init,
+};
+
+static struct platform_device n6q_vwl1271_reg_devices = {
+	.name	= "reg-fixed-voltage",
+	.id	= 4,
+	.dev	= {
+		.platform_data = &n6q_vwl1271_reg_config,
+	},
+};
+
+#endif
+
 void __init board_esdhc_init(char id, int cd_gpio, int wp_gpio)
 {
 #if defined(CONFIG_MACH_MX6Q_PHYFLEX)
@@ -183,9 +255,21 @@ void __init board_esdhc_init(char id, int cd_gpio, int wp_gpio)
 		imx6q_add_sdhci_usdhc_imx(1, &mx6_phytec_sd2_data);
 	} else
 #endif
+
 	if (2 == id) {
+#if !defined(CONFIG_WL12XX)
 		mx6_phytec_sd3_data.cd_gpio = cd_gpio;
 		mx6_phytec_sd3_data.wp_gpio = wp_gpio;
 		imx6q_add_sdhci_usdhc_imx(2, &mx6_phytec_sd3_data);
+#else
+		gpio_request(WLAN_ENABLE, "WLAN Enable");
+		gpio_direction_output(WLAN_ENABLE, 1);
+		wl1271_set_power(0);
+		imx6q_add_sdhci_usdhc_imx(2, &mx6_phytec_sd3_data);
+		/* WL12xx WLAN Init */
+		if (wl12xx_set_platform_data(&n6q_wlan_data))
+		      pr_err("error setting wl12xx data\n");
+		platform_device_register(&n6q_vwl1271_reg_devices);
+#endif
 	}
 }