diff options
| author | Anson Huang <b20788@freescale.com> | 2013-04-18 10:04:56 +0800 |
|---|---|---|
| committer | Anson Huang <b20788@freescale.com> | 2013-04-19 08:54:49 +0800 |
| commit | c3da336af13e6fc18e365237e359675fb57e6901 (patch) | |
| tree | d2ee46679c501f262a41c21dd86a79ddd08e4702 /arch | |
| parent | bdef87471cdfd083c4d44d5ed5ffdc575356e444 (diff) | |
ENGR00259341 mx6: Need to keep WAIT mode fix bit set before standby
According to hardware design requirement, the WAIT mode setting bit17
need to be set if system enter suspend without ARM power gated, so in
standby mode, we can NOT clear this bit.
Signed-off-by: Anson Huang <b20788@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-mx6/system.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-mx6/system.c b/arch/arm/mach-mx6/system.c index 4990a4a0abbb..11038d66caaf 100644 --- a/arch/arm/mach-mx6/system.c +++ b/arch/arm/mach-mx6/system.c @@ -233,7 +233,7 @@ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode) */ reg = __raw_readl(MXC_CCM_CGPR); reg |= MXC_CCM_CGPR_MEM_IPG_STOP_MASK; - if (!cpu_is_mx6sl()) { + if (!cpu_is_mx6sl() && stop_mode >= 2) { /* * For MX6QTO1.2 or later and MX6DLTO1.1 or later, * ensure that the CCM_CGPR bit 17 is cleared before |