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authorTroy Kisky <troy.kisky@boundarydevices.com>2013-05-30 20:10:07 -0700
committerEric Nelson <eric.nelson@boundarydevices.com>2013-06-09 10:56:03 -0700
commit1233c1c72d3d490009587253cdc857e662f0641a (patch)
tree4662b9657c4686e3af1c4ea87e7c16c2f404116e /arch
parent2868a28a3132215b39e20647fd531d2338e10b0f (diff)
msi: fix INT D, when msi is in use(not quite working)
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-mx6/msi.c32
-rw-r--r--arch/arm/mach-mx6/pcie.c4
-rw-r--r--arch/arm/plat-mxc/include/mach/mx6.h3
3 files changed, 36 insertions, 3 deletions
diff --git a/arch/arm/mach-mx6/msi.c b/arch/arm/mach-mx6/msi.c
index 096d1c2494f3..e65f284b60f4 100644
--- a/arch/arm/mach-mx6/msi.c
+++ b/arch/arm/mach-mx6/msi.c
@@ -30,6 +30,7 @@
#define IMX_NUM_MSI_IRQS 128
static DECLARE_BITMAP(msi_irq_in_use, IMX_NUM_MSI_IRQS);
+static int intd_active;
static void imx_msi_handler(unsigned int irq, struct irq_desc *desc)
{
@@ -48,6 +49,10 @@ static void imx_msi_handler(unsigned int irq, struct irq_desc *desc)
}
base_irq += 32;
}
+ if (intd_active) {
+ pr_info("%s intd\n", __func__);
+ generic_handle_irq(MXC_INT_PCIE_0B);
+ }
chained_irq_exit(chip, desc);
}
@@ -145,7 +150,32 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
return 0;
}
+static void intd_irq_mask(struct irq_data *d)
+{
+ pr_info("%s\n", __func__);
+ intd_active = 0;
+}
+
+static void intd_irq_unmask(struct irq_data *d)
+{
+ pr_info("%s\n", __func__);
+ intd_active = 1;
+}
+
+static struct irq_chip intd_irq_chip = {
+ .name = "PCIe intD",
+ .irq_mask = intd_irq_mask,
+ .irq_unmask = intd_irq_unmask,
+};
+
+
void imx_msi_init(void)
{
- irq_set_chained_handler(MXC_INT_PCIE_0, imx_msi_handler);
+ if (pci_msi_enabled()) {
+ int irq = MXC_INT_PCIE_0B;
+ irq_set_chained_handler(MXC_INT_PCIE_0, imx_msi_handler);
+
+ irq_set_chip_and_handler(irq, &intd_irq_chip, handle_simple_irq);
+ set_irq_flags(irq, IRQF_VALID);
+ }
}
diff --git a/arch/arm/mach-mx6/pcie.c b/arch/arm/mach-mx6/pcie.c
index 6f5d7d4f9bfe..7146aea0df8c 100644
--- a/arch/arm/mach-mx6/pcie.c
+++ b/arch/arm/mach-mx6/pcie.c
@@ -540,8 +540,8 @@ static int imx_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
case 1: return MXC_INT_PCIE_3;
case 2: return MXC_INT_PCIE_2;
case 3: return MXC_INT_PCIE_1;
- case 4: return MXC_INT_PCIE_0;
- default: return -1;
+ case 4: return pci_msi_enabled() ? MXC_INT_PCIE_0B : MXC_INT_PCIE_0;
+ default: return -EINVAL;
}
}
diff --git a/arch/arm/plat-mxc/include/mach/mx6.h b/arch/arm/plat-mxc/include/mach/mx6.h
index ba38b8a4181e..bd525dbb6b38 100644
--- a/arch/arm/plat-mxc/include/mach/mx6.h
+++ b/arch/arm/plat-mxc/include/mach/mx6.h
@@ -484,6 +484,9 @@
#define MXC_INT_ANATOP_ANA2 159
#define MXC_INT_END 159
+/* If MSI support is active, this is INT D for a card that doesn't use MSI */
+#define MXC_INT_PCIE_0B 160
+
#define MX6Q_INT_UART1 MXC_INT_UART1_ANDED
#define MX6Q_INT_UART2 MXC_INT_UART2_ANDED
#define MX6Q_INT_UART3 MXC_INT_UART3_ANDED