update by yagi

15 files changed, 378 insertions, 133 deletions

diff --git a/arch/arm/mach-mvf/Makefile b/arch/arm/mach-mvf/Makefile
index 03813026847a..ca85b5ee3769 100644
--- a/arch/arm/mach-mvf/Makefile
+++ b/arch/arm/mach-mvf/Makefile
@@ -3,6 +3,6 @@
 #
 
 # Object file lists.
-obj-y   := mm.o devices.o irq.o clock.o
+obj-y   := mm.o devices.o irq.o clock.o bus_freq.o system.o
 
-#obj-$(MACH_TWR_VF600) += board-twr_vf600.o
+obj-$(CONFIG_MACH_TWR_VF600) += board-twr_vf600.o
diff --git a/arch/arm/mach-mvf/Makefile.boot b/arch/arm/mach-mvf/Makefile.boot
index dc006a84c32c..81a97a400659 100644
--- a/arch/arm/mach-mvf/Makefile.boot
+++ b/arch/arm/mach-mvf/Makefile.boot
@@ -1,3 +1,3 @@
-   zreladdr-$(CONFIG_ARCH_MX6Q)	:= 0x10008000
-params_phys-$(CONFIG_ARCH_MX6Q)	:= 0x10000100
-initrd_phys-$(CONFIG_ARCH_MX6Q)	:= 0x10800000
+   zreladdr-$(CONFIG_ARCH_MVF)	:= 0x80008000
+params_phys-$(CONFIG_ARCH_MVF)	:= 0x80000100
+initrd_phys-$(CONFIG_ARCH_MVF)	:= 0x80800000
diff --git a/arch/arm/mach-mvf/board-twr_vf600.c b/arch/arm/mach-mvf/board-twr_vf600.c
index dc4218ab8fca..a211399604e3 100644
--- a/arch/arm/mach-mvf/board-twr_vf600.c
+++ b/arch/arm/mach-mvf/board-twr_vf600.c
@@ -1,4 +1,6 @@
 /*
+ * based on arch/arm/mach-mx6/board-mx6q_arm2.c
+ *
  * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved.
  *
  * This program is free software; you can redistribute it and/or modify
@@ -35,7 +37,7 @@
 #include <linux/i2c/pca953x.h>
 #include <linux/ata.h>
 #include <linux/mtd/mtd.h>
-#include <linux/mtd/map.h>
+//#include <linux/mtd/map.h>
 #include <linux/mtd/partitions.h>
 #include <linux/pmic_external.h>
 #include <linux/pmic_status.h>
@@ -72,13 +74,13 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 
-#include "usb.h"
-#include "devices-imx6q.h"
+//#include "usb.h"
+#include "devices-vf6xx.h"
 #include "crm_regs.h"
-#include "cpu_op-mx6.h"
-#include "board-mx6q_arm2.h"
-#include "board-mx6dl_arm2.h"
+//#include "cpu_op-mvf.h"
+#include "board-twr_vf600.h"
 
+#if 0 //FIXME
 /* GPIO PIN, sort by PORT/BIT */
 #define MX6_ARM2_LDB_BACKLIGHT		IMX_GPIO_NR(1, 9)
 #define MX6_ARM2_ECSPI1_CS0		IMX_GPIO_NR(2, 30)
@@ -336,7 +338,7 @@ static const struct imxuart_platform_data mx6_arm2_uart1_data __initconst = {
 	.dma_req_tx = MX6Q_DMA_REQ_UART2_TX,
 };
 
-static inline void mx6_arm2_init_uart(void)
+static inline void twr_vf600_init_uart(void)
 {
 	imx6q_add_imx_uart(3, NULL);
 	imx6q_add_imx_uart(1, &mx6_arm2_uart1_data);
@@ -1233,7 +1235,7 @@ static void imx6_arm2_usbotg_vbus(bool on)
 		gpio_set_value(MX6_ARM2_USB_OTG_PWR, 0);
 }
 
-static void __init mx6_arm2_init_usb(void)
+static void __init twr_vf600_init_usb(void)
 {
 	int ret = 0;
 
@@ -1774,7 +1776,7 @@ static struct platform_device mx6_arm2_audio_device = {
 	.name = "imx-sgtl5000",
 };
 
-static int __init mx6_arm2_init_audio(void)
+static int __init twr_vf600_init_audio(void)
 {
 	struct clk *pll3_pfd, *esai_clk;
 	mxc_register_device(&sab_audio_device, &sab_audio_data);
@@ -1862,12 +1864,14 @@ static struct mxc_dvfs_platform_data arm2_dvfscore_data = {
 	.dncnt_val		= 10,
 	.delay_time		= 80,
 };
+#endif //FIXME
 
-static void __init mx6_arm2_fixup(struct machine_desc *desc, struct tag *tags,
+static void __init twr_vf600_fixup(struct machine_desc *desc, struct tag *tags,
 				   char **cmdline, struct meminfo *mi)
 {
 }
 
+#if 0 //FIXME
 static int __init early_enable_sgtl5000(char *p)
 {
 	sgtl5000_en = 1;
@@ -1929,12 +1933,14 @@ static int __init early_disable_mipi_dsi(char *p)
 }
 
 early_param("disable_mipi_dsi", early_disable_mipi_dsi);
+#endif //FIXME
 
 /*!
  * Board specific initialization.
  */
-static void __init mx6_arm2_init(void)
+static void __init twr_vf600_init(void)
 {
+#if 0 //FIXME
 	int i;
 	int ret;
 
@@ -2029,7 +2035,7 @@ static void __init mx6_arm2_init(void)
 	 */
 
 	gp_reg_id = arm2_dvfscore_data.reg_id;
-	mx6_arm2_init_uart();
+	twr_vf600_init_uart();
 	imx6q_add_mipi_csi2(&mipi_csi2_pdata);
 	imx6q_add_mxc_hdmi_core(&hdmi_core_data);
 
@@ -2090,8 +2096,8 @@ static void __init mx6_arm2_init(void)
 	if (cpu_is_mx6q())
 		imx6q_add_ahci(0, &mx6_arm2_sata_data);
 	imx6q_add_vpu();
-	mx6_arm2_init_usb();
-	mx6_arm2_init_audio();
+	twr_vf600_init_usb();
+	twr_vf600_init_audio();
 	platform_device_register(&arm2_vmmc_reg_devices);
 	mx6_cpu_regulator_init();
 
@@ -2154,27 +2160,32 @@ static void __init mx6_arm2_init(void)
 		mxc_register_device(&max17135_sensor_device, NULL);
 		imx6dl_add_imx_epdc(&epdc_data);
 	}
+#endif
 }
 
-extern void __iomem *twd_base;
-static void __init mx6_timer_init(void)
+//extern void __iomem *twd_base;
+static void __init mvf_timer_init(void)
 {
 	struct clk *uart_clk;
+#if 0 //FIXME
 #ifdef CONFIG_LOCAL_TIMERS
 	twd_base = ioremap(LOCAL_TWD_ADDR, SZ_256);
 	BUG_ON(!twd_base);
 #endif
-	mx6_clocks_init(32768, 24000000, 0, 0);
+#endif
+	mvf_clocks_init(128000, 24000000, 32000, 24000000);
 
+	//FIXME
 	uart_clk = clk_get_sys("imx-uart.0", NULL);
-	early_console_setup(UART4_BASE_ADDR, uart_clk);
+	early_console_setup(MVF_UART0_BASE_ADDR, uart_clk);
 }
 
 static struct sys_timer mxc_timer = {
-	.init   = mx6_timer_init,
+	.init   = mvf_timer_init,
 };
 
-static void __init mx6_arm2_reserve(void)
+#if 0 //FIXME
+static void __init twr_vf600_reserve(void)
 {
 	phys_addr_t phys;
 
@@ -2186,13 +2197,14 @@ static void __init mx6_arm2_reserve(void)
 		imx6_gpu_pdata.reserved_mem_base = phys;
 	}
 }
+#endif
 
-MACHINE_START(MX6Q_ARM2, "Freescale i.MX 6Quad/Solo/DualLite Armadillo2 Board")
-	.boot_params	= MX6_PHYS_OFFSET + 0x100,
-	.fixup		= mx6_arm2_fixup,
-	.map_io		= mx6_map_io,
-	.init_irq	= mx6_init_irq,
-	.init_machine	= mx6_arm2_init,
+MACHINE_START(TWR_VF600, "Freescale MVF TWR-VF600 Board")
+	.boot_params	= MVF_PHYS_OFFSET + 0x100,
+	.fixup		= twr_vf600_fixup,
+	.map_io		= mvf_map_io,
+	.init_irq	= mvf_init_irq,
+	.init_machine	= twr_vf600_init,
 	.timer		= &mxc_timer,
-	.reserve	= mx6_arm2_reserve,
+	//.reserve	= twr_vf600_reserve,
 MACHINE_END
diff --git a/arch/arm/mach-mvf/board-twr_vf600.h b/arch/arm/mach-mvf/board-twr_vf600.h
index 21c050baf4b1..25d50ef1f980 100644
--- a/arch/arm/mach-mvf/board-twr_vf600.h
+++ b/arch/arm/mach-mvf/board-twr_vf600.h
@@ -16,9 +16,9 @@
  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  */
 
-#include <mach/iomux-vfxx.h>
+#include <mach/iomux-vf6xx.h>
 
-static iomux_v3_cfg_t vf6xx_arm2_pads[] = {
+static iomux_vmvf_cfg_t twr_vf6xx_pads[] = {
 	/* primary function */
 	VF6XX_PAD_PAD_0__CCM_RMII_CLKIN,
 	VF6XX_PAD_PAD_1__DEBUG_TCLK,
@@ -122,7 +122,7 @@ static iomux_v3_cfg_t vf6xx_arm2_pads[] = {
 	VF6XX_PAD_PAD_99__NFC_MLC_NF_RB_B,
 	VF6XX_PAD_PAD_100__NFC_MLC_NF_ALE,
 	VF6XX_PAD_PAD_101__NFC_MLC_NF_CLE,
-,
+	/*FIXME VF6XX_PAD_PAD_102__XXX,*/
 	VF6XX_PAD_PAD_103__ADC0_DA_ADC0SE5,
 	VF6XX_PAD_PAD_104__ADC1_DA_ADC1SE5,
 	VF6XX_PAD_PAD_105__TCON0_TCON1,
diff --git a/arch/arm/mach-mvf/bus_freq.c b/arch/arm/mach-mvf/bus_freq.c
index 36308c14c8f2..482b35139fff 100644
--- a/arch/arm/mach-mvf/bus_freq.c
+++ b/arch/arm/mach-mvf/bus_freq.c
@@ -1,4 +1,6 @@
 /*
+ * based on arch/arm/mach-mx6/bus_freq.c
+ *
  * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
  *
  * This program is free software; you can redistribute it and/or modify
@@ -92,10 +94,12 @@ struct completion voltage_change_cmpl;
 int low_freq_bus_used(void);
 void set_ddr_freq(int ddr_freq);
 
+#if 0
 extern struct cpu_op *(*get_cpu_op)(int *op);
 extern void __iomem *ccm_base;
 extern void __iomem *databahn_base;
 extern int update_ddr_freq(int ddr_rate);
+#endif
 
 
 struct mutex bus_freq_mutex;
@@ -113,7 +117,7 @@ int set_high_bus_freq(int high_bus_freq)
 	return 0;
 }
 
-void exit_lpapm_mode_mx6q(int high_bus_freq)
+void exit_lpapm_mode_mvf(int high_bus_freq)
 {
 
 }
diff --git a/arch/arm/mach-mvf/clock.c b/arch/arm/mach-mvf/clock.c
index ad7b159d097d..4ded93a880bd 100644
--- a/arch/arm/mach-mvf/clock.c
+++ b/arch/arm/mach-mvf/clock.c
@@ -48,7 +48,7 @@ extern struct regulator *cpu_regulator;
 extern struct cpu_op *(*get_cpu_op)(int *op);
 extern int lp_high_freq;
 extern int lp_med_freq;
-#if 0
+#if 0 //FIXME
 extern int vf6xx_revision(void);
 #endif
 
@@ -1117,13 +1117,11 @@ static unsigned long _clk_audio_video_round_rate(struct clk *clk,
 						unsigned long rate)
 {
 	//FIXME: need TEST_DIV_SEL support?
-	unsigned int div, post_div = 1;
+	unsigned int div;
 	unsigned int mfn, mfd = 1000000;
 	s64 temp64;
 	unsigned int parent_rate = clk_get_rate(clk->parent);
 	unsigned long pre_div_rate;
-	u32 test_div_sel = 2;
-	u32 control3 = 0;
 	unsigned long final_rate;
 
 	if (rate < AUDIO_VIDEO_MIN_CLK_FREQ)
@@ -1196,7 +1194,6 @@ static struct clk pll6_video_main_clk = {
 static unsigned long _clk_pll6_div_get_rate(struct clk *clk)
 {
 	unsigned int div;
-	u32 reg;
 
 	div = (__raw_readl(MXC_CCM_CACRR) &~MXC_CCM_CACRR_PLL6_CLK_DIV) >>
 		MXC_CCM_CACRR_PLL6_CLK_DIV_OFFSET;
@@ -1205,7 +1202,7 @@ static unsigned long _clk_pll6_div_get_rate(struct clk *clk)
 	return clk_get_rate(clk->parent) / div;
 }
 
-static int _clk_pll6_div_set_rate(struct clk *clk)
+static int _clk_pll6_div_set_rate(struct clk *clk, unsigned long rate)
 {
 	u32 reg, div;
 	u32 parent_rate;
@@ -1214,7 +1211,7 @@ static int _clk_pll6_div_set_rate(struct clk *clk)
 	div = parent_rate / rate;
 
 	if (div == 0)
-		div == 1;
+		div = 1;
 	if (((parent_rate / div) != rate) || div > 2)
 		return -1;
 
@@ -1777,7 +1774,7 @@ static struct clk can0_clk[] = {
 
 static int _clk_can1_root_enable(struct clk *clk)
 {
-	u32 req;
+	u32 reg;
 
 	reg = __raw_readl(MXC_CCM_CSCDR2) | MXC_CCM_CSCDR2_CAN1_EN;
 	__raw_writel(reg, MXC_CCM_CSCDR2);
@@ -1807,7 +1804,7 @@ static int _clk_can1_root_set_parent(struct clk *clk, struct clk *parent)
 	return 0;
 }
 
-static struct clk can1_root_clk = {
+static struct clk can1_clk_root = {
 	__INIT_CLK_DEBUG(can1_root_clk)
 	.parent = &ips_bus_clk,
 	.enable = _clk_can1_root_enable,
@@ -1871,7 +1868,7 @@ static int _clk_ftm_enable(struct clk *clk)
 {
 	u32 reg;
 
-	reg = __raw_readl(MXC_CCM_CSCDR1) | (1 << clk->enable_shif);
+	reg = __raw_readl(MXC_CCM_CSCDR1) | (1 << clk->enable_shift);
 	__raw_writel(reg, MXC_CCM_CSCDR1);
 
 	return 0;
@@ -1881,7 +1878,7 @@ static void _clk_ftm_disable(struct clk *clk)
 {
 	u32 reg;
 
-	reg = __raw_readl(MXC_CCM_CSCDR1) & ~(1 << clk->enable_shif);
+	reg = __raw_readl(MXC_CCM_CSCDR1) & ~(1 << clk->enable_shift);
 	__raw_writel(reg, MXC_CCM_CSCDR1);
 }
 
@@ -1910,7 +1907,7 @@ static int _clk_ftm_ext_set_parent(struct clk *clk, struct clk *parent)
 	else
 		return -EINVAL;
 
-	mux = _get_mux(parent, &ckil_clk, &oscl_clk, &osch_clk, &audio_ext_clk);
+	mux = _get_mux(parent, &ckil_clk, &oscl_clk, &osch_clk, &audio_ext);
 	reg = __raw_readl(MXC_CCM_CSCMR2) & ~(0x3 << shift);
 	reg |= mux << shift;
 	__raw_writel(reg, MXC_CCM_CSCMR2);
@@ -1940,7 +1937,7 @@ static int _clk_ftm_fix_set_parent(struct clk *clk, struct clk *parent)
 	else if (parent == &ckil_clk)
 		mux = 1;
 	else
-		return -EINVAL
+		return -EINVAL;
 
 	reg = __raw_readl(MXC_CCM_CSCMR2) & ~(1 << shift);
 	reg |= mux << shift;
@@ -1952,7 +1949,7 @@ static int _clk_ftm_fix_set_parent(struct clk *clk, struct clk *parent)
 static struct clk ftm0_ext_clk = {
 	__INIT_CLK_DEBUG(ftm0_ext_clk)
 	.parent = &ckil_clk,
-	.enable_shift = MXC_CCM_CSCDR1_FTM0_CLK_EN_OFFSET;
+	.enable_shift = MXC_CCM_CSCDR1_FTM0_CLK_EN_OFFSET,
 	.enable = _clk_ftm_enable,
 	.disable = _clk_ftm_disable,
 	.get_rate = _clk_ftm_ext_get_rate,
@@ -1962,7 +1959,7 @@ static struct clk ftm0_ext_clk = {
 static struct clk ftm1_ext_clk = {
 	__INIT_CLK_DEBUG(ftm1_ext_clk)
 	.parent = &ckil_clk,
-	.enable_shift = MXC_CCM_CSCDR1_FTM1_CLK_EN_OFFSET;
+	.enable_shift = MXC_CCM_CSCDR1_FTM1_CLK_EN_OFFSET,
 	.enable = _clk_ftm_enable,
 	.disable = _clk_ftm_disable,
 	.get_rate = _clk_ftm_ext_get_rate,
@@ -1972,7 +1969,7 @@ static struct clk ftm1_ext_clk = {
 static struct clk ftm2_ext_clk = {
 	__INIT_CLK_DEBUG(ftm2_ext_clk)
 	.parent = &ckil_clk,
-	.enable_shift = MXC_CCM_CSCDR1_FTM2_CLK_EN_OFFSET;
+	.enable_shift = MXC_CCM_CSCDR1_FTM2_CLK_EN_OFFSET,
 	.enable = _clk_ftm_enable,
 	.disable = _clk_ftm_disable,
 	.get_rate = _clk_ftm_ext_get_rate,
@@ -1982,7 +1979,7 @@ static struct clk ftm2_ext_clk = {
 static struct clk ftm3_ext_clk = {
 	__INIT_CLK_DEBUG(ftm3_ext_clk)
 	.parent = &ckil_clk,
-	.enable_shift = MXC_CCM_CSCDR1_FTM3_CLK_EN_OFFSET;
+	.enable_shift = MXC_CCM_CSCDR1_FTM3_CLK_EN_OFFSET,
 	.enable = _clk_ftm_enable,
 	.disable = _clk_ftm_disable,
 	.get_rate = _clk_ftm_ext_get_rate,
@@ -1992,37 +1989,37 @@ static struct clk ftm3_ext_clk = {
 static struct clk ftm0_fix_clk = {
 	__INIT_CLK_DEBUG(ftm0_fix_clk)
 	.parent = &oscl_clk,
-	.enable_shift = MXC_CCM_CSCDR1_FTM0_CLK_EN_OFFSET;
+	.enable_shift = MXC_CCM_CSCDR1_FTM0_CLK_EN_OFFSET,
 	.enable = _clk_ftm_enable,
 	.disable = _clk_ftm_disable,
-	.set_parent = _clk_ftm0_fix_set_parent,
+	.set_parent = _clk_ftm_fix_set_parent,
 };
 
 static struct clk ftm1_fix_clk = {
 	__INIT_CLK_DEBUG(ftm1_fix_clk)
 	.parent = &oscl_clk,
-	.enable_shift = MXC_CCM_CSCDR1_FTM1_CLK_EN_OFFSET;
+	.enable_shift = MXC_CCM_CSCDR1_FTM1_CLK_EN_OFFSET,
 	.enable = _clk_ftm_enable,
 	.disable = _clk_ftm_disable,
-	.set_parent = _clk_ftm1_fix_set_parent,
+	.set_parent = _clk_ftm_fix_set_parent,
 };
 
 static struct clk ftm2_fix_clk = {
 	__INIT_CLK_DEBUG(ftm2_fix_clk)
 	.parent = &oscl_clk,
-	.enable_shift = MXC_CCM_CSCDR1_FTM2_CLK_EN_OFFSET;
+	.enable_shift = MXC_CCM_CSCDR1_FTM2_CLK_EN_OFFSET,
 	.enable = _clk_ftm_enable,
 	.disable = _clk_ftm_disable,
-	.set_parent = _clk_ftm2_fix_set_parent,
+	.set_parent = _clk_ftm_fix_set_parent,
 };
 
 static struct clk ftm3_fix_clk = {
 	__INIT_CLK_DEBUG(ftm3_fix_clk)
 	.parent = &oscl_clk,
-	.enable_shift = MXC_CCM_CSCDR1_FTM3_CLK_EN_OFFSET;
+	.enable_shift = MXC_CCM_CSCDR1_FTM3_CLK_EN_OFFSET,
 	.enable = _clk_ftm_enable,
 	.disable = _clk_ftm_disable,
-	.set_parent = _clk_ftm3_fix_set_parent,
+	.set_parent = _clk_ftm_fix_set_parent,
 };
 
 static int _clk_ftm0_set_parent(struct clk *clk, struct clk *parent)
@@ -2049,7 +2046,7 @@ static int _clk_ftm0_set_parent(struct clk *clk, struct clk *parent)
 }
 
 static struct clk ftm0_clk = {
-	__INIT_CLK_DEBUG(ftm0_clk),
+	__INIT_CLK_DEBUG(ftm0_clk)
 	.parent = &ftm0_fix_clk, //FIXME
 	.enable_reg = MXC_CCM_CCGR1,
 	.enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
@@ -2082,7 +2079,7 @@ static int _clk_ftm1_set_parent(struct clk *clk, struct clk *parent)
 }
 
 static struct clk ftm1_clk = {
-	__INIT_CLK_DEBUG(ftm1_clk),
+	__INIT_CLK_DEBUG(ftm1_clk)
 	.parent = &ftm1_fix_clk, //FIXME
 	.enable_reg = MXC_CCM_CCGR1,
 	.enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
@@ -2115,7 +2112,7 @@ static int _clk_ftm2_set_parent(struct clk *clk, struct clk *parent)
 }
 
 static struct clk ftm2_clk = {
-	__INIT_CLK_DEBUG(ftm2_clk),
+	__INIT_CLK_DEBUG(ftm2_clk)
 	.parent = &ftm2_fix_clk, //FIXME
 	.enable_reg = MXC_CCM_CCGR7,
 	.enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
@@ -2148,7 +2145,7 @@ static int _clk_ftm3_set_parent(struct clk *clk, struct clk *parent)
 }
 
 static struct clk ftm3_clk = {
-	__INIT_CLK_DEBUG(ftm3_clk),
+	__INIT_CLK_DEBUG(ftm3_clk)
 	.parent = &ftm3_fix_clk, //FIXME
 	.enable_reg = MXC_CCM_CCGR7,
 	.enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
@@ -2157,7 +2154,7 @@ static struct clk ftm3_clk = {
 	.set_parent = _clk_ftm3_set_parent,
 };
 
-static int _clk_enet_rmii_enable(truct clk *clk)
+static int _clk_enet_rmii_enable(struct clk *clk)
 {
 	u32 reg;
 
@@ -2189,7 +2186,7 @@ static int _clk_enet_rmii_set_parent(struct clk *clk, struct clk *parent)
 }
 
 static struct clk enet_rmii_clk = {
-	__INIT_CLK_DEBUG(enet_rmii_clk),
+	__INIT_CLK_DEBUG(enet_rmii_clk)
 	.parent = &enet_ext,
 	.enable = _clk_enet_rmii_enable,
 	.disable = _clk_enet_rmii_disable,
@@ -2198,11 +2195,11 @@ static struct clk enet_rmii_clk = {
 #endif
 };
 
-static int _clk_enet_ts_enable(truct clk *clk)
+static int _clk_enet_ts_enable(struct clk *clk)
 {
 	u32 reg;
 
-	reg = __raw_readl(MXC_CCM_CSCDR1) | MXC_CCM_CSCDR1_TS_CLK_EN;
+	reg = __raw_readl(MXC_CCM_CSCDR1) | MXC_CCM_CSCDR1_ENET_TS_EN;
 	__raw_writel(reg, MXC_CCM_CSCDR1);
 
 	return 0;
@@ -2212,7 +2209,7 @@ static void _clk_enet_ts_disable(struct clk *clk)
 {
 	u32 reg;
 
-	reg = __raw_readl(MXC_CCM_CSCDR1) & ~MXC_CCM_CSCDR1_TS_CLK_EN;
+	reg = __raw_readl(MXC_CCM_CSCDR1) & ~MXC_CCM_CSCDR1_ENET_TS_EN;
 	__raw_writel(reg, MXC_CCM_CSCDR1);
 }
 
@@ -2246,7 +2243,7 @@ static int _clk_enet_ts_set_parent(struct clk *clk, struct clk *parent)
 }
 
 static struct clk enet_ts_clk = {
-	__INIT_CLK_DEBUG(enet_ts_clk),
+	__INIT_CLK_DEBUG(enet_ts_clk)
 	.parent = &enet_ext,
 	.enable = _clk_enet_ts_enable,
 	.disable = _clk_enet_ts_disable,
@@ -2269,7 +2266,7 @@ static int _clk_dcu_enable(struct clk *clk)
 	return 0;
 }
 
-static int _clk_dcu_disable(struct clk *clk)
+static void _clk_dcu_disable(struct clk *clk)
 {
 	u32 reg;
 
@@ -2278,7 +2275,7 @@ static int _clk_dcu_disable(struct clk *clk)
 	__raw_writel(reg, MXC_CCM_CSCDR3);
 }
 
-static unsigned long _clk_dcu_get_rate(struct clk *clk, unsigned long rate)
+static unsigned long _clk_dcu_get_rate(struct clk *clk)
 {
 	u32 reg, div;
 
@@ -2286,11 +2283,9 @@ static unsigned long _clk_dcu_get_rate(struct clk *clk, unsigned long rate)
 	if (clk == &dcu0_clk_root)
 		div = ((reg & ~MXC_CCM_CSCDR3_DCU0_DIV_MASK) >>
 			MXC_CCM_CSCDR3_DCU0_DIV_OFFSET) + 1;
-	else if (clk == &dcu1_clk_root)
+	else
 		div = ((reg & ~MXC_CCM_CSCDR3_DCU1_DIV_MASK) >>
 			MXC_CCM_CSCDR3_DCU1_DIV_OFFSET) + 1;
-	else
-		return -EINVAL;
 
 	return clk_get_rate(clk->parent) / div;
 }
@@ -2315,6 +2310,7 @@ static int _clk_dcu_set_rate(struct clk *clk, unsigned long rate)
 		reg |= (div -1) << MXC_CCM_CSCDR3_DCU1_DIV_OFFSET;
 	} else
 		return -EINVAL;
+
 	__raw_writel(reg, MXC_CCM_CSCDR3);
 
 	return 0;
@@ -2335,13 +2331,14 @@ static int _clk_dcu_set_parent(struct clk *clk, struct clk *parent)
 		reg |= mux << MXC_CCM_CSCMR1_DCU1_CLK_SEL_OFFSET;
 	} else
 		return -EINVAL;
+
 	__raw_writel(reg, MXC_CCM_CSCMR1);
 
 	return 0;
 }
 
 static struct clk dcu0_clk_root = {
-	__INIT_CLK_DEBUG(dcu0_clk_root),
+	__INIT_CLK_DEBUG(dcu0_clk_root)
 	.parent = &pll1_pfd2, //FIXME
 	.enable_shift = MXC_CCM_CSCDR3_DCU0_EN_OFFSET,
 	.enable = _clk_dcu_enable,
@@ -2351,9 +2348,9 @@ static struct clk dcu0_clk_root = {
 	.set_parent = _clk_dcu_set_parent,
 };
 
-static struct dcu0_clk[] = {
+static struct clk dcu0_clk[] = {
 	{
-	__INIT_CLK_DEBUG(dcu0_clk_0),
+	__INIT_CLK_DEBUG(dcu0_clk_0)
 	.id = 0,
 	.parent = &dcu0_clk_root,
 	.enable_reg = MXC_CCM_CCGR3,
@@ -2363,7 +2360,7 @@ static struct dcu0_clk[] = {
 	.secondary = &dcu0_clk[1],
 	},
 	{
-	__INIT_CLK_DEBUG(dcu0_clk_1),
+	__INIT_CLK_DEBUG(dcu0_clk_1)
 	.id = 1,
 	.parent = &dcu0_clk_root,
 	.enable_reg = MXC_CCM_CCGR3,
@@ -2373,7 +2370,7 @@ static struct dcu0_clk[] = {
 	.secondary = &dcu0_clk[2],
 	},
 	{
-	__INIT_CLK_DEBUG(dcu0_clk_2),
+	__INIT_CLK_DEBUG(dcu0_clk_2)
 	.id = 2,
 	.parent = &dcu0_clk_root,
 	.enable_reg = MXC_CCM_CCGR3,
@@ -2383,7 +2380,7 @@ static struct dcu0_clk[] = {
 	.secondary = &dcu0_clk[3],
 	},
 	{
-	__INIT_CLK_DEBUG(dcu0_clk_3),
+	__INIT_CLK_DEBUG(dcu0_clk_3)
 	.id = 3,
 	.parent = &dcu0_clk_root,
 	.enable_reg = MXC_CCM_CCGR3,
@@ -2393,7 +2390,7 @@ static struct dcu0_clk[] = {
 	.secondary = &dcu0_clk[4],
 	},
 	{
-	__INIT_CLK_DEBUG(dcu0_clk_4),
+	__INIT_CLK_DEBUG(dcu0_clk_4)
 	.id = 4,
 	.parent = &dcu0_clk_root,
 	.enable_reg = MXC_CCM_CCGR3,
@@ -2403,7 +2400,7 @@ static struct dcu0_clk[] = {
 	.secondary = &dcu0_clk[5],
 	},
 	{
-	__INIT_CLK_DEBUG(dcu0_clk_5),
+	__INIT_CLK_DEBUG(dcu0_clk_5)
 	.id = 5,
 	.parent = &dcu0_clk_root,
 	.enable_reg = MXC_CCM_CCGR3,
@@ -2413,7 +2410,7 @@ static struct dcu0_clk[] = {
 	.secondary = &dcu0_clk[6],
 	},
 	{
-	__INIT_CLK_DEBUG(dcu0_clk_6),
+	__INIT_CLK_DEBUG(dcu0_clk_6)
 	.id = 6,
 	.parent = &dcu0_clk_root,
 	.enable_reg = MXC_CCM_CCGR3,
@@ -2423,7 +2420,7 @@ static struct dcu0_clk[] = {
 	.secondary = &dcu0_clk[7],
 	},
 	{
-	__INIT_CLK_DEBUG(dcu0_clk_7),
+	__INIT_CLK_DEBUG(dcu0_clk_7)
 	.id = 7,
 	.parent = &dcu0_clk_root,
 	.enable_reg = MXC_CCM_CCGR3,
@@ -2431,10 +2428,10 @@ static struct dcu0_clk[] = {
 	.enable = _clk_enable,
 	.disable = _clk_disable,
 	},
-}
+};
 
 static struct clk dcu1_clk_root = {
-	__INIT_CLK_DEBUG(dcu1_clk_root),
+	__INIT_CLK_DEBUG(dcu1_clk_root)
 	.parent = &pll1_pfd2, //FIXME
 	.enable_shift = MXC_CCM_CSCDR3_DCU1_EN_OFFSET,
 	.enable = _clk_dcu_enable,
@@ -2446,7 +2443,7 @@ static struct clk dcu1_clk_root = {
 
 static struct clk dcu1_clk[] = {
 	{
-	__INIT_CLK_DEBUG(dcu1_clk_0),
+	__INIT_CLK_DEBUG(dcu1_clk_0)
 	.id = 0,
 	.parent = &dcu1_clk_root,
 	.enable_reg = MXC_CCM_CCGR9,
@@ -2456,7 +2453,7 @@ static struct clk dcu1_clk[] = {
 	.secondary = &dcu1_clk[1],
 	},
 	{
-	__INIT_CLK_DEBUG(dcu1_clk_1),
+	__INIT_CLK_DEBUG(dcu1_clk_1)
 	.id = 1,
 	.parent = &dcu1_clk_root,
 	.enable_reg = MXC_CCM_CCGR9,
@@ -2466,7 +2463,7 @@ static struct clk dcu1_clk[] = {
 	.secondary = &dcu1_clk[2],
 	},
 	{
-	__INIT_CLK_DEBUG(dcu1_clk_2),
+	__INIT_CLK_DEBUG(dcu1_clk_2)
 	.id = 2,
 	.parent = &dcu1_clk_root,
 	.enable_reg = MXC_CCM_CCGR9,
@@ -2476,7 +2473,7 @@ static struct clk dcu1_clk[] = {
 	.secondary = &dcu1_clk[3],
 	},
 	{
-	__INIT_CLK_DEBUG(dcu1_clk_3),
+	__INIT_CLK_DEBUG(dcu1_clk_3)
 	.id = 3,
 	.parent = &dcu1_clk_root,
 	.enable_reg = MXC_CCM_CCGR9,
@@ -2486,7 +2483,7 @@ static struct clk dcu1_clk[] = {
 	.secondary = &dcu1_clk[4],
 	},
 	{
-	__INIT_CLK_DEBUG(dcu1_clk_4),
+	__INIT_CLK_DEBUG(dcu1_clk_4)
 	.id = 4,
 	.parent = &dcu1_clk_root,
 	.enable_reg = MXC_CCM_CCGR9,
@@ -2496,7 +2493,7 @@ static struct clk dcu1_clk[] = {
 	.secondary = &dcu1_clk[5],
 	},
 	{
-	__INIT_CLK_DEBUG(dcu1_clk_5),
+	__INIT_CLK_DEBUG(dcu1_clk_5)
 	.id = 5,
 	.parent = &dcu1_clk_root,
 	.enable_reg = MXC_CCM_CCGR9,
@@ -2506,7 +2503,7 @@ static struct clk dcu1_clk[] = {
 	.secondary = &dcu1_clk[6],
 	},
 	{
-	__INIT_CLK_DEBUG(dcu1_clk_6),
+	__INIT_CLK_DEBUG(dcu1_clk_6)
 	.id = 6,
 	.parent = &dcu1_clk_root,
 	.enable_reg = MXC_CCM_CCGR9,
@@ -2516,7 +2513,7 @@ static struct clk dcu1_clk[] = {
 	.secondary = &dcu1_clk[7],
 	},
 	{
-	__INIT_CLK_DEBUG(dcu1_clk_7),
+	__INIT_CLK_DEBUG(dcu1_clk_7)
 	.id = 7,
 	.parent = &dcu1_clk_root,
 	.enable_reg = MXC_CCM_CCGR9,
@@ -2531,20 +2528,20 @@ static int _clk_video_adc_enable(struct clk *clk)
 	u32 reg;
 
 	reg = __raw_readl(MXC_CCM_CSCDR1) | MXC_CCM_CSCDR1_VADC_EN;
-	_raw_writel(reg, MXC_CCM_CSCDR1);
+	__raw_writel(reg, MXC_CCM_CSCDR1);
 
 	_clk_enable(clk);
 	return 0;
 }
 
-static void _clk_video_adc__disable(struct clk *clk)
+static void _clk_video_adc_disable(struct clk *clk)
 {
 	u32 reg;
 
 	_clk_disable(clk);
 
 	reg = __raw_readl(MXC_CCM_CSCDR1) & ~MXC_CCM_CSCDR1_VADC_EN;
-	_raw_writel(reg, MXC_CCM_CSCDR1);
+	__raw_writel(reg, MXC_CCM_CSCDR1);
 }
 
 static unsigned long _clk_video_adc_get_rate(struct clk *clk)
@@ -2557,7 +2554,7 @@ static unsigned long _clk_video_adc_get_rate(struct clk *clk)
 	return clk_get_rate(clk->parent) / (div + 1);
 }
 
-tatic int _clk_video_adc_set_rate(struct clk *clk, unsigned long rate)
+static int _clk_video_adc_set_rate(struct clk *clk, unsigned long rate)
 {
 	u32 reg, div;
 	u32 parent_rate = clk_get_rate(clk->parent);
@@ -2592,7 +2589,7 @@ static int _clk_video_adc_set_parent(struct clk *clk, struct clk *parent)
 }
 
 static struct clk video_adc_clk = {
-	__INIT_CLK_DEBUG(video_adc_clk),
+	__INIT_CLK_DEBUG(video_adc_clk)
 	.parent = &pll6_div_clk, //FIXME
 	.enable_reg = MXC_CCM_CCGR8,
 	.enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
@@ -2609,7 +2606,7 @@ static unsigned long _clk_video_adc_div2_get_rate(struct clk *clk)
 }
 
 static struct clk video_adc_div2_clk = {
-	__INIT_CLK_DEBUG(video_adc_div2_clk),
+	__INIT_CLK_DEBUG(video_adc_div2_clk)
 	.parent = &video_adc_clk,
 	.get_rate = _clk_video_adc_div2_get_rate,
 };
@@ -2619,7 +2616,7 @@ static int _clk_gpu_enable(struct clk *clk)
 	u32 reg;
 
 	reg = __raw_readl(MXC_CCM_CSCDR2) | MXC_CCM_CSCDR2_GPU_EN;
-	_raw_writel(reg, MXC_CCM_CSCDR2);
+	__raw_writel(reg, MXC_CCM_CSCDR2);
 
 	_clk_enable(clk);
 	return 0;
@@ -2632,7 +2629,7 @@ static void _clk_gpu_disable(struct clk *clk)
 	_clk_disable(clk);
 
 	reg = __raw_readl(MXC_CCM_CSCDR2) & ~MXC_CCM_CSCDR2_GPU_EN;
-	_raw_writel(reg, MXC_CCM_CSCDR2);
+	__raw_writel(reg, MXC_CCM_CSCDR2);
 }
 
 static int _clk_gpu_set_parent(struct clk *clk, struct clk *parent)
@@ -2640,7 +2637,7 @@ static int _clk_gpu_set_parent(struct clk *clk, struct clk *parent)
 	int mux;
 	u32 reg;
 
-	mux = _get_mux(parent, &pll2_pfd2, &pll3_pfd2, &NULL, NULL);
+	mux = _get_mux(parent, &pll2_pfd2, &pll3_pfd2, NULL, NULL);
 
 	reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_GPU_CLK_SEL;
 	reg |= mux << MXC_CCM_CSCMR1_GPU_CLK_SEL_OFFSET;
@@ -2651,14 +2648,12 @@ static int _clk_gpu_set_parent(struct clk *clk, struct clk *parent)
 }
 
 static struct clk gpu_clk = {
-	__INIT_CLK_DEBUG(gpu_clk),
+	__INIT_CLK_DEBUG(gpu_clk)
 	.parent = &pll2_pfd2, //FIXME
 	.enable_reg = MXC_CCM_CCGR8,
 	.enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
 	.enable = _clk_gpu_enable,
 	.disable = _clk_gpu_disable,
-	.get_rate = _clk_gpu_get_rate,
-	.set_rate = _clk_gpu_set_rate,
 	.set_parent = _clk_gpu_set_parent,
 };
 
@@ -3009,7 +3004,7 @@ static struct clk eth_l2_sw_clk[] = {
 	.enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
 	.enable = _clk_enable,
 	.disable = _clk_disable,
-	.secondary = eth_l2_sw_clk[1],
+	.secondary = &eth_l2_sw_clk[1],
 	},
 	{
 	__INIT_CLK_DEBUG(eth_l2_sw_1_clk)
@@ -3019,7 +3014,7 @@ static struct clk eth_l2_sw_clk[] = {
 	.enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
 	.enable = _clk_enable,
 	.disable = _clk_disable,
-	.secondary = eth_l2_sw_clk[2],
+	.secondary = &eth_l2_sw_clk[2],
 	},
 	{
 	__INIT_CLK_DEBUG(eth_l2_sw_2_clk)
@@ -3029,7 +3024,7 @@ static struct clk eth_l2_sw_clk[] = {
 	.enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
 	.enable = _clk_enable,
 	.disable = _clk_disable,
-	.secondary = eth_l2_sw_clk[3],
+	.secondary = &eth_l2_sw_clk[3],
 	},
 	{
 	__INIT_CLK_DEBUG(eth_l2_sw_3_clk)
@@ -3039,7 +3034,7 @@ static struct clk eth_l2_sw_clk[] = {
 	.enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
 	.enable = _clk_enable,
 	.disable = _clk_disable,
-	.secondary = eth_l2_sw_clk[4],
+	.secondary = &eth_l2_sw_clk[4],
 	},
 	{
 	__INIT_CLK_DEBUG(eth_l2_sw_4_clk)
@@ -3049,7 +3044,7 @@ static struct clk eth_l2_sw_clk[] = {
 	.enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
 	.enable = _clk_enable,
 	.disable = _clk_disable,
-	.secondary = eth_l2_sw_clk[5],
+	.secondary = &eth_l2_sw_clk[5],
 	},
 	{
 	__INIT_CLK_DEBUG(eth_l2_sw_5_clk)
@@ -3059,7 +3054,7 @@ static struct clk eth_l2_sw_clk[] = {
 	.enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
 	.enable = _clk_enable,
 	.disable = _clk_disable,
-	.secondary = eth_l2_sw_clk[6],
+	.secondary = &eth_l2_sw_clk[6],
 	},
 	{
 	__INIT_CLK_DEBUG(eth_l2_sw_6_clk)
@@ -3069,7 +3064,7 @@ static struct clk eth_l2_sw_clk[] = {
 	.enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
 	.enable = _clk_enable,
 	.disable = _clk_disable,
-	.secondary = eth_l2_sw_clk[7],
+	.secondary = &eth_l2_sw_clk[7],
 	},
 	{
 	__INIT_CLK_DEBUG(eth_l2_sw_7_clk)
@@ -3272,7 +3267,7 @@ static void clk_tree_init(void)
 		break;
 	}
 
-	mux = (__raw_readl(MXC_CCM_CCSR) & MXC_CCM_CCSR_CA5_CLK_SEL_MASK)
+	mux = (__raw_readl(MXC_CCM_CCSR) & MXC_CCM_CCSR_CA5_CLK_SEL)
 		>> MXC_CCM_CCSR_CA5_CLK_SEL_OFFSET;
 	switch (mux) {
 	case 0:
@@ -3385,8 +3380,6 @@ int __init mvf_clocks_init(unsigned long ckil, unsigned long ckih,
 	pll_480_usb2_main_clk.disable(&pll_480_usb2_main_clk);
 	pll5_enet_main_clk.disable(&pll5_enet_main_clk);
 
-	sata_clk[0].disable(&sata_clk[0]);
-	pcie_clk[0].disable(&pcie_clk[0]);
 
 	/* Initialize Audio and Video PLLs to valid frequency (650MHz). */
 	clk_set_rate(&pll4_audio_main_clk, 650000000);
@@ -3431,7 +3424,7 @@ int __init mvf_clocks_init(unsigned long ckil, unsigned long ckih,
 		     3 << MXC_CCM_CCPGRx_PPCG12_OFFSET |
 		     3 << MXC_CCM_CCPGRx_PPCG14_OFFSET,
 		     MXC_CCM_CCPGR2);
-	__raw_writel(3 << MXC_CCM_CCPGRx_PPCG0_OFFSET,
+	__raw_writel(3 << MXC_CCM_CCPGRx_PPCG0_OFFSET |
 		     3 << MXC_CCM_CCPGRx_PPCG1_OFFSET |
 		     3 << MXC_CCM_CCPGRx_PPCG2_OFFSET |
 		     3 << MXC_CCM_CCPGRx_PPCG3_OFFSET |
@@ -3573,8 +3566,10 @@ int __init mvf_clocks_init(unsigned long ckil, unsigned long ckih,
 		     3 << MXC_CCM_CCGRx_CG8_OFFSET,
 		     MXC_CCM_CCGR11);
 
+#if 0 //FIXME
 	base = ioremap(MVF_PIT_BASE_ADDR, SZ_4K);
-	mxc_timer_init(&pit_clk, base, MXC_INT_PIT);
+	mvf_timer_init(&pit_clk, base, MXC_INT_PIT);
+#endif
 
 	lp_high_freq = 0;
 	lp_med_freq = 0;
diff --git a/arch/arm/mach-mvf/crm_regs.h b/arch/arm/mach-mvf/crm_regs.h
index bf923f355174..fd0919d283e6 100644
--- a/arch/arm/mach-mvf/crm_regs.h
+++ b/arch/arm/mach-mvf/crm_regs.h
@@ -212,7 +212,7 @@
 #define MXC_CCM_CCSR_CA5_CLK_SEL		(1 << 3)
 #define MXC_CCM_CCSR_CA5_CLK_SEL_OFFSET		(3)
 #define MXC_CCM_CCSR_SYS_CLK_SEL_MASK		(0x7)
-#define MXC_CCM_CCSR_SYS_CLK_SE_OFFSET		(0)
+#define MXC_CCM_CCSR_SYS_CLK_SEL_OFFSET		(0)
 
 /* Define the bits in register CACRR */
 #define MXC_CCM_CACRR_FLEX_CLK_DIV_MASK		(0x7 << 22)
@@ -274,7 +274,7 @@
 #define MXC_CCM_CSCDR1_FTM0_CLK_EN		(1 << 25)
 #define MXC_CCM_CSCDR1_FTM0_CLK_EN_OFFSET	(25)
 #define MXC_CCM_CSCDR1_RMII_CLK_EN		(1 << 24)
-#define MXC_CCM_CSCDR1_ENET_ST_EN		(1 << 23)
+#define MXC_CCM_CSCDR1_ENET_TS_EN		(1 << 23)
 #define MXC_CCM_CSCDR1_VADC_EN			(1 << 22)
 #define MXC_CCM_CSCDR1_VADC_DIV_MASK		(0x3 << 20)
 #define MXC_CCM_CSCDR1_VADC_DIV_OFFSET		(20)
@@ -344,9 +344,13 @@
 #define MXC_CCM_CSCMR2_SWO_CLK_SEL		(1 << 19)
 #define MXC_CCM_CSCMR2_TRACE_CLK_SEL		(1 << 18)
 #define MXC_CCM_CSCMR2_FTM3_FIX_CLK_SEL		(1 << 17)
+#define MXC_CCM_CSCMR2_FTM3_FIX_CLK_SEL_OFFSET	(17)
 #define MXC_CCM_CSCMR2_FTM2_FIX_CLK_SEL		(1 << 16)
+#define MXC_CCM_CSCMR2_FTM2_FIX_CLK_SEL_OFFSET	(16)
 #define MXC_CCM_CSCMR2_FTM1_FIX_CLK_SEL		(1 << 15)
+#define MXC_CCM_CSCMR2_FTM1_FIX_CLK_SEL_OFFSET	(15)
 #define MXC_CCM_CSCMR2_FTM0_FIX_CLK_SEL		(1 << 14)
+#define MXC_CCM_CSCMR2_FTM0_FIX_CLK_SEL_OFFSET	(14)
 #define MXC_CCM_CSCMR2_FTM3_EXT_CLK_SEL_MASK	(0x3 << 12)
 #define MXC_CCM_CSCMR2_FTM3_EXT_CLK_SEL_OFFSET	(12)
 #define MXC_CCM_CSCMR2_FTM2_EXT_CLK_SEL_MASK	(0x3 << 10)
diff --git a/arch/arm/mach-mvf/devices-vf6xx.h b/arch/arm/mach-mvf/devices-vf6xx.h
new file mode 100644
index 000000000000..19534fecfc6d
--- /dev/null
+++ b/arch/arm/mach-mvf/devices-vf6xx.h
@@ -0,0 +1,212 @@
+/*
+ * based on arch/arm/mach-mx6/devices-imx6q.h
+ *
+ * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <mach/mvf.h>
+#include <mach/devices-common.h>
+
+extern const struct imx_imx_uart_1irq_data imx6q_imx_uart_data[] __initconst;
+#define imx6q_add_imx_uart(id, pdata)	\
+	imx_add_imx_uart_1irq(&imx6q_imx_uart_data[id], pdata)
+
+extern const struct imx_snvs_rtc_data imx6q_imx_snvs_rtc_data __initconst;
+#define imx6q_add_imx_snvs_rtc()	\
+	imx_add_snvs_rtc(&imx6q_imx_snvs_rtc_data)
+
+extern const struct imx_anatop_thermal_imx_data
+imx6q_anatop_thermal_imx_data __initconst;
+#define imx6q_add_anatop_thermal_imx(id, pdata)	\
+	imx_add_anatop_thermal_imx(&imx6q_anatop_thermal_imx_data, pdata)
+
+extern const struct imx_dma_data imx6q_dma_data __initconst;
+#define imx6q_add_dma()	imx_add_dma(&imx6q_dma_data);
+
+#define imx6q_add_gpmi(platform_data)	imx_add_gpmi(platform_data);
+
+extern const struct imx_fec_data imx6q_fec_data __initconst;
+#define imx6q_add_fec(pdata)	\
+	imx_add_fec(&imx6q_fec_data, pdata)
+
+extern const struct imx_sdhci_esdhc_imx_data
+imx6q_sdhci_usdhc_imx_data[] __initconst;
+#define imx6q_add_sdhci_usdhc_imx(id, pdata)	\
+	imx_add_sdhci_esdhc_imx(&imx6q_sdhci_usdhc_imx_data[id], pdata)
+
+extern const struct imx_spi_imx_data imx6q_ecspi_data[] __initconst;
+#define imx6q_add_ecspi(id, pdata)	\
+	imx_add_spi_imx(&imx6q_ecspi_data[id], pdata)
+
+extern const struct imx_imx_i2c_data imx6q_imx_i2c_data[] __initconst;
+#define imx6q_add_imx_i2c(id, pdata)	\
+	imx_add_imx_i2c(&imx6q_imx_i2c_data[id], pdata)
+
+extern const struct imx_fsl_usb2_udc_data imx6q_fsl_usb2_udc_data __initconst;
+#define imx6q_add_fsl_usb2_udc(pdata)	\
+	imx_add_fsl_usb2_udc(&imx6q_fsl_usb2_udc_data, pdata)
+
+extern const struct imx_mxc_ehci_data imx6q_mxc_ehci_otg_data __initconst;
+#define imx6q_add_fsl_ehci_otg(pdata)	\
+	imx_add_fsl_ehci(&imx6q_mxc_ehci_otg_data, pdata)
+
+extern const struct imx_mxc_ehci_data imx6q_mxc_ehci_hs_data[] __initconst;
+#define imx6q_add_fsl_ehci_hs(id, pdata)	\
+	imx_add_fsl_ehci(&imx6q_mxc_ehci_hs_data[id - 1], pdata)
+
+extern const struct imx_fsl_usb2_otg_data imx6q_fsl_usb2_otg_data __initconst;
+#define imx6q_add_fsl_usb2_otg(pdata)	\
+	imx_add_fsl_usb2_otg(&imx6q_fsl_usb2_otg_data, pdata)
+
+extern const struct imx_fsl_usb2_wakeup_data imx6q_fsl_otg_wakeup_data __initconst;
+#define imx6q_add_fsl_usb2_otg_wakeup(pdata)	\
+	imx_add_fsl_usb2_wakeup(&imx6q_fsl_otg_wakeup_data, pdata)
+
+extern const struct imx_fsl_usb2_wakeup_data imx6q_fsl_hs_wakeup_data[] __initconst;
+#define imx6q_add_fsl_usb2_hs_wakeup(id, pdata)	\
+	imx_add_fsl_usb2_wakeup(&imx6q_fsl_hs_wakeup_data[id - 1], pdata)
+
+extern const struct imx_imx_esai_data imx6q_imx_esai_data[] __initconst;
+#define imx6q_add_imx_esai(id, pdata) \
+	imx_add_imx_esai(&imx6q_imx_esai_data[id], pdata)
+
+extern const struct imx_viv_gpu_data imx6_gpu_data __initconst;
+
+extern const struct imx_ahci_data imx6q_ahci_data __initconst;
+#define imx6q_add_ahci(id, pdata)   \
+	imx_add_ahci(&imx6q_ahci_data, pdata)
+
+extern const struct imx_imx_ssi_data imx6_imx_ssi_data[] __initconst;
+#define imx6q_add_imx_ssi(id, pdata)            \
+	imx_add_imx_ssi(&imx6_imx_ssi_data[id], pdata)
+
+extern const struct imx_ipuv3_data imx6q_ipuv3_data[] __initconst;
+#define imx6q_add_ipuv3(id, pdata)	imx_add_ipuv3(id, &imx6q_ipuv3_data[id], pdata)
+#define imx6q_add_ipuv3fb(id, pdata)	imx_add_ipuv3_fb(id, pdata)
+
+#define imx6q_add_lcdif(pdata)	\
+	platform_device_register_resndata(NULL, "mxc_lcdif",\
+			0, NULL, 0, pdata, sizeof(*pdata));
+
+extern const struct imx_ldb_data imx6q_ldb_data __initconst;
+#define imx6q_add_ldb(pdata) \
+	imx_add_ldb(&imx6q_ldb_data, pdata);
+
+#define imx6q_add_v4l2_output(id)	\
+	platform_device_register_resndata(NULL, "mxc_v4l2_output",\
+			id, NULL, 0, NULL, 0);
+
+#define imx6q_add_v4l2_capture(id)	\
+	platform_device_register_resndata(NULL, "mxc_v4l2_capture",\
+			id, NULL, 0, NULL, 0);
+
+extern const struct imx_mxc_hdmi_data imx6q_mxc_hdmi_data __initconst;
+#define imx6q_add_mxc_hdmi(pdata)	\
+	imx_add_mxc_hdmi(&imx6q_mxc_hdmi_data, pdata)
+
+extern const struct imx_mxc_hdmi_core_data imx6q_mxc_hdmi_core_data __initconst;
+#define imx6q_add_mxc_hdmi_core(pdata)	\
+	imx_add_mxc_hdmi_core(&imx6q_mxc_hdmi_core_data, pdata)
+
+extern const struct imx_vpu_data imx6q_vpu_data __initconst;
+#define imx6q_add_vpu() imx_add_vpu(&imx6q_vpu_data)
+
+extern const struct imx_otp_data imx6q_otp_data __initconst;
+#define imx6q_add_otp() \
+	imx_add_otp(&imx6q_otp_data)
+
+extern const struct imx_viim_data imx6q_viim_data __initconst;
+#define imx6q_add_viim() \
+	imx_add_viim(&imx6q_viim_data)
+
+extern const struct imx_imx2_wdt_data imx6q_imx2_wdt_data[] __initconst;
+#define imx6q_add_imx2_wdt(id, pdata)   \
+	imx_add_imx2_wdt(&imx6q_imx2_wdt_data[id])
+
+extern const struct imx_pm_imx_data imx6q_pm_imx_data __initconst;
+#define imx6q_add_pm_imx(id, pdata)	\
+	imx_add_pm_imx(&imx6q_pm_imx_data, pdata)
+
+extern const struct imx_imx_asrc_data imx6q_imx_asrc_data[] __initconst;
+#define imx6q_add_asrc(pdata)	\
+	imx_add_imx_asrc(imx6q_imx_asrc_data, pdata)
+
+extern const struct imx_spi_imx_data imx6q_ecspi_data[] __initconst;
+#define imx6q_add_ecspi(id, pdata)      \
+	imx_add_spi_imx(&imx6q_ecspi_data[id], pdata)
+
+extern const struct imx_dvfs_core_data imx6q_dvfs_core_data __initconst;
+#define imx6q_add_dvfs_core(pdata)	\
+	imx_add_dvfs_core(&imx6q_dvfs_core_data, pdata)
+
+extern const struct imx_viv_gpu_data imx6_gc2000_data __initconst;
+extern const struct imx_viv_gpu_data imx6_gc320_data __initconst;
+extern const struct imx_viv_gpu_data imx6_gc355_data __initconst;
+
+extern const struct imx_mxc_pwm_data imx6q_mxc_pwm_data[] __initconst;
+#define imx6q_add_mxc_pwm(id)	\
+	imx_add_mxc_pwm(&imx6q_mxc_pwm_data[id])
+
+#define imx6q_add_mxc_pwm_backlight(id, pdata)	   \
+	platform_device_register_resndata(NULL, "pwm-backlight",\
+			id, NULL, 0, pdata, sizeof(*pdata));
+
+extern const struct imx_spdif_data imx6q_imx_spdif_data __initconst;
+#define imx6q_add_spdif(pdata)	imx_add_spdif(&imx6q_imx_spdif_data, pdata)
+
+extern const struct imx_spdif_dai_data imx6q_spdif_dai_data __initconst;
+#define imx6q_add_spdif_dai()	imx_add_spdif_dai(&imx6q_spdif_dai_data)
+
+#define imx6q_add_spdif_audio_device(pdata)	imx_add_spdif_audio_device()
+
+#define imx6q_add_hdmi_soc() imx_add_hdmi_soc()
+extern const struct imx_hdmi_soc_data imx6q_imx_hdmi_soc_dai_data __initconst;
+#define imx6q_add_hdmi_soc_dai() \
+	imx_add_hdmi_soc_dai(&imx6q_imx_hdmi_soc_dai_data)
+
+extern const struct imx_mipi_dsi_data imx6q_mipi_dsi_data __initconst;
+#define imx6q_add_mipi_dsi(pdata)	\
+	imx_add_mipi_dsi(&imx6q_mipi_dsi_data, pdata)
+
+extern const struct imx_flexcan_data imx6q_flexcan_data[] __initconst;
+#define imx6q_add_flexcan(id, pdata)	\
+	imx_add_flexcan(&imx6q_flexcan_data[id], pdata)
+#define imx6q_add_flexcan0(pdata)	imx6q_add_flexcan(0, pdata)
+#define imx6q_add_flexcan1(pdata)	imx6q_add_flexcan(1, pdata)
+
+extern const struct imx_mipi_csi2_data imx6q_mipi_csi2_data __initconst;
+#define imx6q_add_mipi_csi2(pdata)	\
+	imx_add_mipi_csi2(&imx6q_mipi_csi2_data, pdata)
+
+extern const struct imx_perfmon_data imx6q_perfmon_data[] __initconst;
+#define imx6q_add_perfmon(id) \
+	imx_add_perfmon(&imx6q_perfmon_data[id])
+
+extern const struct imx_mxc_mlb_data imx6q_mxc_mlb150_data __initconst;
+#define imx6q_add_mlb150(pdata)        \
+	imx_add_mlb(pdata)
+
+extern const struct imx_pxp_data imx6dl_pxp_data __initconst;
+#define imx6dl_add_imx_pxp()   \
+	imx_add_imx_pxp(&imx6dl_pxp_data)
+
+#define imx6dl_add_imx_pxp_client()   \
+	imx_add_imx_pxp_client()
+
+extern const struct imx_epdc_data imx6dl_epdc_data __initconst;
+#define imx6dl_add_imx_epdc(pdata)	\
+	imx_add_imx_epdc(&imx6dl_epdc_data, pdata)
diff --git a/arch/arm/mach-mvf/devices.c b/arch/arm/mach-mvf/devices.c
index dcb41aba7110..82c4fb21abba 100644
--- a/arch/arm/mach-mvf/devices.c
+++ b/arch/arm/mach-mvf/devices.c
@@ -81,5 +81,9 @@ static struct mvf_gpio_port mvf_gpio_ports[] = {
 int mvf_register_gpios(void)
 {
 	/* 5 ports for MVF */
+#if 0
 	return mvf_gpio_init(mvf_gpio_ports, 7);
+#else
+	return 0;
+#endif
 }
diff --git a/arch/arm/mach-mvf/mm.c b/arch/arm/mach-mvf/mm.c
index 5c3f4cfdfc43..62afa4ab92d3 100644
--- a/arch/arm/mach-mvf/mm.c
+++ b/arch/arm/mach-mvf/mm.c
@@ -28,8 +28,7 @@
 
 #include <mach/hardware.h>
 #include <mach/common.h>
-//#include <mach/iomux-vf.h>
-//#include <asm/hardware/cache-l2x0.h>
+#include <asm/hardware/cache-l2x0.h>
 
 /*!
  * This structure defines the Faraday memory map.
@@ -58,7 +57,9 @@ void __init mvf_map_io(void)
 	mxc_iomux_vmvf_init(MVF_IO_ADDRESS(MVF_IOMUXC_BASE_ADDR));
 	mxc_arch_reset_init(MVF_IO_ADDRESS(MVF_WDOC_A5_BASE_ADDR));
 	mvf_set_cpu_type();
+#if 0
 	mxc_cpu_lp_set(WAIT_CLOCKED);
+#endif
 }
 
 #ifdef CONFIG_CACHE_L2X0
@@ -66,18 +67,18 @@ int mxc_init_l2x0(void)
 {
 	unsigned int val;
 
-	writel(0x132, IO_ADDRESS(L2_BASE_ADDR + L2X0_TAG_LATENCY_CTRL));
-	writel(0x132, IO_ADDRESS(L2_BASE_ADDR + L2X0_DATA_LATENCY_CTRL));
+	writel(0x132, MVF_IO_ADDRESS(MVF_CA5_L2C_BASE_ADDR + L2X0_TAG_LATENCY_CTRL));
+	writel(0x132, MVF_IO_ADDRESS(MVF_CA5_L2C_BASE_ADDR + L2X0_DATA_LATENCY_CTRL));
 
-	val = readl(IO_ADDRESS(L2_BASE_ADDR + L2X0_PREFETCH_CTRL));
+	val = readl(MVF_IO_ADDRESS(MVF_CA5_L2C_BASE_ADDR + L2X0_PREFETCH_CTRL));
 	val |= 0x40800000;
-	writel(val, IO_ADDRESS(L2_BASE_ADDR + L2X0_PREFETCH_CTRL));
-	val = readl(IO_ADDRESS(L2_BASE_ADDR + L2X0_POWER_CTRL));
+	writel(val, MVF_IO_ADDRESS(MVF_CA5_L2C_BASE_ADDR + L2X0_PREFETCH_CTRL));
+	val = readl(MVF_IO_ADDRESS(MVF_CA5_L2C_BASE_ADDR + L2X0_POWER_CTRL));
 	val |= L2X0_DYNAMIC_CLK_GATING_EN;
 	val |= L2X0_STNDBY_MODE_EN;
-	writel(val, IO_ADDRESS(L2_BASE_ADDR + L2X0_POWER_CTRL));
+	writel(val, MVF_IO_ADDRESS(MVF_CA5_L2C_BASE_ADDR + L2X0_POWER_CTRL));
 
-	l2x0_init(IO_ADDRESS(L2_BASE_ADDR), 0x0, ~0x00000000);
+	l2x0_init(MVF_IO_ADDRESS(MVF_CA5_L2C_BASE_ADDR), 0x0, ~0x00000000);
 	return 0;
 }
 
diff --git a/arch/arm/mach-mvf/system.c b/arch/arm/mach-mvf/system.c
index 0eb6592969dd..7feca9297700 100644
--- a/arch/arm/mach-mvf/system.c
+++ b/arch/arm/mach-mvf/system.c
@@ -1,4 +1,6 @@
 /*
+ * based on arch/arm/mach-mx6/system.c
+ *
  * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved.
  *
  * This program is free software; you can redistribute it and/or modify
@@ -30,6 +32,7 @@
 #include "crm_regs.h"
 #include "regs-anadig.h"
 
+#if 0
 #define SCU_CTRL					0x00
 #define SCU_CONFIG					0x04
 #define SCU_CPU_STATUS				0x08
@@ -155,9 +158,11 @@ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
 	}
 	__raw_writel(ccm_clpcr, MXC_CCM_CLPCR);
 }
+#endif
 
  void arch_idle(void)
 {
+#if 0
 	if (enable_wait_mode) {
 		if ((num_online_cpus() == num_present_cpus())
 			&& mx6_wait_in_iram != NULL) {
@@ -168,9 +173,11 @@ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
 				cpu_do_idle();
 		}
 	} else
+#endif
 		cpu_do_idle();
 }
 
+#if 0
 static int __mxs_reset_block(void __iomem *hwreg, int just_enable)
 {
 	u32 c;
@@ -265,3 +272,4 @@ int mxs_reset_block(void __iomem *hwreg)
 	return _mxs_reset_block(hwreg, false);
 }
 EXPORT_SYMBOL(mxs_reset_block);
+#endif
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 9df1154ae622..b6f3d8df13dd 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -821,7 +821,8 @@ config CACHE_L2X0
 	depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
 		   REALVIEW_EB_A9MP || SOC_IMX35 || SOC_IMX31 || MACH_REALVIEW_PBX || \
 		   ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \
-		   ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || SOC_IMX6Q
+		   ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || SOC_IMX6Q || \
+		   SOC_VF6XX
 	default y
 	select OUTER_CACHE
 	select OUTER_CACHE_SYNC
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 89bc884873f8..a6bdc638a2e4 100755
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -35,6 +35,7 @@ extern void mx51_map_io(void);
 extern void mx53_map_io(void);
 extern void mx6_map_io(void);
 extern void mxc91231_map_io(void);
+extern void mvf_map_io(void);
 extern void imx1_init_early(void);
 extern void imx21_init_early(void);
 extern void imx25_init_early(void);
@@ -58,6 +59,7 @@ extern void mx51_init_irq(void);
 extern void mx53_init_irq(void);
 extern void mx6_init_irq(void);
 extern void mxc91231_init_irq(void);
+extern void mvf_init_irq(void);
 extern void epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq);
 extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int);
 extern int mx1_clocks_init(unsigned long fref);
@@ -76,6 +78,8 @@ extern int mx6_clocks_init(unsigned long ckil, unsigned long osc,
 			unsigned long ckih1, unsigned long ckih2);
 extern void imx6_init_fec(struct fec_platform_data fec_data);
 extern int mxc91231_clocks_init(unsigned long fref);
+extern int mvf_clocks_init(unsigned long ckil, unsigned long ckih,
+			unsigned long oscl, unsigned long osch);
 extern int mxc_register_gpios(void);
 extern int mxc_register_device(struct platform_device *pdev, void *data);
 extern void mxc_set_cpu_type(unsigned int type);
diff --git a/arch/arm/plat-mxc/include/mach/iomux-vf6xx.h b/arch/arm/plat-mxc/include/mach/iomux-vf6xx.h
index ac59b9e6082a..b0520eb6c032 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-vf6xx.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-vf6xx.h
@@ -2091,7 +2091,6 @@ typedef enum iomux_config {
 		(_VF6XX_PAD_PAD_18__ESDHC1_DAT2 | MUX_CTRL_PAD(NO_PAD_CTRL))	
 #define VF6XX_PAD_PAD_18__TCON1_TCON8			\
 		(_VF6XX_PAD_PAD_18__TCON1_TCON8 | MUX_CTRL_PAD(NO_PAD_CTRL))	
-#define VF6XX_PAD_PAD_9__QUADSPI1_QSCK_A			\
 
 #define VF6XX_PAD_PAD_19__RGPIOC_GPIO19			\
 		(_VF6XX_PAD_PAD_19__RGPIOC_GPIO19 | MUX_CTRL_PAD(NO_PAD_CTRL))	
diff --git a/arch/arm/plat-mxc/include/mach/mvf.h b/arch/arm/plat-mxc/include/mach/mvf.h
index 1112a1cabc1f..7f95d93b049c 100644
--- a/arch/arm/plat-mxc/include/mach/mvf.h
+++ b/arch/arm/plat-mxc/include/mach/mvf.h
@@ -387,6 +387,7 @@
 #define MXC_INT_GPIOE			153
 #define MXC_INT_END			153
 
+#define IRQ_GLOBALTIMER			27
 #define IRQ_LOCALTIMER			29
 
 /*