diff options
| author | Andreas Färber <afaerber@suse.de> | 2014-11-06 18:22:10 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2014-11-14 10:10:40 -0800 |
| commit | 7322a1dde616aa0e031192fc98a1c6e85bcef424 (patch) | |
| tree | c654b8139efe65fe28128d7c5bff3f9108ff5361 /arch | |
| parent | 4199f74e534522d099bffb33c2896090493eee8d (diff) | |
ARM: dts: zynq: Enable PL clocks for Parallella
commit 92c9e0c780e61f821ab8a08f0d4d4fd33ba1197c upstream.
The Parallella board comes with a U-Boot bootloader that loads one of
two predefined FPGA bitstreams before booting the kernel. Both define an
AXI interface to the on-board Epiphany processor.
Enable clocks FCLK0..FCLK3 for the Programmable Logic by default.
Otherwise accessing, e.g., the ESYSRESET register freezes the board,
as seen with the Epiphany SDK tools e-reset and e-hw-rev, using /dev/mem.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/zynq-parallella.dts | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts index 41afd9da6876..229140b6de64 100644 --- a/arch/arm/boot/dts/zynq-parallella.dts +++ b/arch/arm/boot/dts/zynq-parallella.dts @@ -34,6 +34,10 @@ }; }; +&clkc { + fclk-enable = <0xf>; +}; + &gem0 { status = "okay"; phy-mode = "rgmii-id"; |