diff options
| author | Adrian Alonso <aalonso@freescale.com> | 2015-06-04 14:14:55 -0500 |
|---|---|---|
| committer | Adrian Alonso <aalonso@freescale.com> | 2015-06-10 15:05:37 -0500 |
| commit | a50846f7e3cbd99c63275abd3d2dbfb33b805446 (patch) | |
| tree | 1304cb9a7175ed42dba49d8a8571d8d8847c5c6a /arch | |
| parent | d9d19231b257a183a13df450e365a2a847d997eb (diff) | |
MLK-11046: arm: imx: clk-imx7d: add adc_root_clk
* Add ADC root clock IMX7D_ADC_ROOT_CLK
* Update device tree adc node to use IMX7D_ADC_ROOT_CLK
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/imx7d.dtsi | 4 | ||||
| -rw-r--r-- | arch/arm/mach-imx/clk-imx7d.c | 1 |
2 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index 04f7ac10f79d..8d6d3a17d7f6 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -680,7 +680,7 @@ compatible = "fsl,imx7d-adc"; reg = <0x30610000 0x10000>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_CLK_DUMMY>; + clocks = <&clks IMX7D_ADC_ROOT_CLK>; num-channels = <4>; clock-names = "adc"; status = "disabled"; @@ -690,7 +690,7 @@ compatible = "fsl,imx7d-adc"; reg = <0x30620000 0x10000>; interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_CLK_DUMMY>; + clocks = <&clks IMX7D_ADC_ROOT_CLK>; num-channels = <4>; clock-names = "adc"; status = "disabled"; diff --git a/arch/arm/mach-imx/clk-imx7d.c b/arch/arm/mach-imx/clk-imx7d.c index ea99d42ad731..d76087143e9b 100644 --- a/arch/arm/mach-imx/clk-imx7d.c +++ b/arch/arm/mach-imx/clk-imx7d.c @@ -860,6 +860,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) clks[IMX7D_USB_CTRL_CLK] = imx_clk_gate4("usb_ctrl_clk", "ahb_root_clk", base + 0x4680, 0); clks[IMX7D_USB_PHY1_CLK] = imx_clk_gate4("usb_phy1_clk", "pll_usb1_main_clk", base + 0x46a0, 0); clks[IMX7D_USB_PHY2_CLK] = imx_clk_gate4("usb_phy2_clk", "pll_usb_main_clk", base + 0x46b0, 0); + clks[IMX7D_ADC_ROOT_CLK] = imx_clk_gate4("adc_root_clk", "ipg_root_clk", base + 0x4200, 0); clks[IMX7D_GPT_3M_CLK] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8); |