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authorAlex Frid <afrid@nvidia.com>2013-07-11 19:50:22 -0700
committerHarshada Kale <hkale@nvidia.com>2013-09-12 02:22:02 -0700
commitdbb6882a58b47f6af22d964bf873fb427a951877 (patch)
treeea1ab0f7ea7524ab213024ca5d67458dd22ae80f /arch
parent655edcabad1c17a9258857b447f379ee66126bcf (diff)
ARM: tegra11: dvfs: Update T40T tables and limits
Updated dvfs and edp tables, clock and voltage limits for T40T part. Change-Id: Ic256a6f3aa8026c96443ecc33204309275fcbe2e Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/250032 (cherry picked from commit d4add7fa3c1f5d26cb3a39e3431ca7c3fdb849e4) Reviewed-on: http://git-master/r/253672 Tested-by: Shaoming Feng <shaomingf@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-tegra/tegra11_clocks.c8
-rw-r--r--arch/arm/mach-tegra/tegra11_dvfs.c126
-rw-r--r--arch/arm/mach-tegra/tegra11_edp.c4
-rw-r--r--arch/arm/mach-tegra/tegra11_speedo.c2
4 files changed, 71 insertions, 69 deletions
diff --git a/arch/arm/mach-tegra/tegra11_clocks.c b/arch/arm/mach-tegra/tegra11_clocks.c
index d94679697b8f..bb7a0cabfd24 100644
--- a/arch/arm/mach-tegra/tegra11_clocks.c
+++ b/arch/arm/mach-tegra/tegra11_clocks.c
@@ -6329,7 +6329,7 @@ static struct clk tegra_clk_c2bus = {
.name = "c2bus",
.parent = &tegra_pll_c2,
.ops = &tegra_clk_cbus_ops,
- .max_rate = 700000000,
+ .max_rate = 864000000,
.mul = 1,
.div = 1,
.flags = PERIPH_ON_CBUS,
@@ -6539,11 +6539,11 @@ struct clk tegra_list_clks[] = {
PERIPH_CLK("uartc_dbg", "serial8250.0", "uartc", 55, 0x1a0, 408000000, mux_pllp_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
PERIPH_CLK("uartd_dbg", "serial8250.0", "uartd", 65, 0x1c0, 408000000, mux_pllp_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
PERIPH_CLK("uarte_dbg", "serial8250.0", "uarte", 66, 0x1c4, 408000000, mux_pllp_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
- PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 700000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
- PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 700000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE),
+ PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 864000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
+ PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 864000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE),
PERIPH_CLK_EX("vi", "vi", "vi", 20, 0x148, 425000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops),
PERIPH_CLK("vi_sensor", "vi", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET),
- PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 700000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT),
+ PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 864000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT),
#ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
PERIPH_CLK("msenc", "msenc", NULL, 60, 0x170, 600000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
#else
diff --git a/arch/arm/mach-tegra/tegra11_dvfs.c b/arch/arm/mach-tegra/tegra11_dvfs.c
index 7490d2bcd1b6..8b7ac870817b 100644
--- a/arch/arm/mach-tegra/tegra11_dvfs.c
+++ b/arch/arm/mach-tegra/tegra11_dvfs.c
@@ -254,7 +254,7 @@ static struct dvfs cpu_dvfs = {
/* Core DVFS tables */
/* FIXME: real data */
static const int core_millivolts[MAX_DVFS_FREQS] = {
- 900, 950, 1000, 1050, 1100, 1120, 1170, 1200, 1250};
+ 900, 950, 1000, 1050, 1100, 1120, 1170, 1200, 1250, 1390};
#define CORE_DVFS(_clk_name, _speedo_id, _process_id, _auto, _mult, _freqs...) \
{ \
@@ -269,80 +269,80 @@ static const int core_millivolts[MAX_DVFS_FREQS] = {
}
static struct dvfs core_dvfs_table[] = {
- /* Core voltages (mV): 900, 950, 1000, 1050, 1100, 1120, 1170, 1200, 1250 */
+ /* Core voltages (mV): 900, 950, 1000, 1050, 1100, 1120, 1170, 1200, 1250, 1390 */
/* Clock limits for internal blocks, PLLs */
#ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
- CORE_DVFS("emc", -1, -1, 1, KHZ, 1, 1, 1, 1, 800000, 800000, 933000, 933000, 1066000),
+ CORE_DVFS("emc", -1, -1, 1, KHZ, 1, 1, 1, 1, 800000, 800000, 933000, 933000, 1066000, 1066000),
- CORE_DVFS("cpu_lp", 0, 0, 1, KHZ, 228000, 306000, 396000, 510000, 648000, 696000, 696000, 696000, 696000),
- CORE_DVFS("cpu_lp", 0, 1, 1, KHZ, 324000, 396000, 510000, 612000, 696000, 696000, 696000, 696000, 696000),
- CORE_DVFS("cpu_lp", 1, 1, 1, KHZ, 324000, 396000, 510000, 612000, 768000, 816000, 816000, 816000, 816000),
+ CORE_DVFS("cpu_lp", 0, 0, 1, KHZ, 228000, 306000, 396000, 528000, 648000, 696000, 696000, 696000, 696000, 696000),
+ CORE_DVFS("cpu_lp", 0, 1, 1, KHZ, 324000, 432000, 528000, 612000, 696000, 696000, 696000, 696000, 696000, 696000),
+ CORE_DVFS("cpu_lp", 1, 1, 1, KHZ, 324000, 432000, 528000, 612000, 792000, 816000, 816000, 816000, 816000, 816000),
- CORE_DVFS("sbus", 0, 0, 1, KHZ, 132000, 188000, 240000, 276000, 324000, 336000, 336000, 336000, 336000),
- CORE_DVFS("sbus", 0, 1, 1, KHZ, 180000, 228000, 300000, 336000, 336000, 336000, 336000, 336000, 336000),
- CORE_DVFS("sbus", 1, 1, 1, KHZ, 180000, 228000, 300000, 336000, 372000, 384000, 384000, 384000, 384000),
+ CORE_DVFS("sbus", 0, 0, 1, KHZ, 132000, 188000, 240000, 276000, 324000, 336000, 336000, 336000, 336000, 336000),
+ CORE_DVFS("sbus", 0, 1, 1, KHZ, 180000, 228000, 300000, 336000, 336000, 336000, 336000, 336000, 336000, 336000),
+ CORE_DVFS("sbus", 1, 1, 1, KHZ, 180000, 228000, 300000, 336000, 372000, 384000, 384000, 384000, 384000, 384000),
- CORE_DVFS("vi", -1, 0, 1, KHZ, 144000, 216000, 240000, 312000, 372000, 408000, 408000, 408000, 408000),
- CORE_DVFS("vi", -1, 1, 1, KHZ, 144000, 216000, 240000, 408000, 408000, 408000, 408000, 408000, 408000),
+ CORE_DVFS("vi", -1, 0, 1, KHZ, 144000, 216000, 240000, 312000, 372000, 408000, 408000, 408000, 408000, 408000),
+ CORE_DVFS("vi", -1, 1, 1, KHZ, 144000, 216000, 240000, 408000, 408000, 408000, 408000, 408000, 408000, 408000),
- CORE_DVFS("2d", -1, 0, 1, KHZ, 192000, 228000, 300000, 396000, 492000, 516000, 552000, 552000, 600000),
- CORE_DVFS("3d", -1, 0, 1, KHZ, 192000, 228000, 300000, 396000, 492000, 516000, 552000, 552000, 600000),
- CORE_DVFS("epp", -1, 0, 1, KHZ, 192000, 228000, 300000, 396000, 492000, 516000, 552000, 552000, 600000),
+ CORE_DVFS("2d", -1, 0, 1, KHZ, 192000, 228000, 300000, 396000, 492000, 516000, 552000, 552000, 600000, 600000),
+ CORE_DVFS("3d", -1, 0, 1, KHZ, 192000, 228000, 300000, 396000, 492000, 516000, 552000, 552000, 600000, 600000),
+ CORE_DVFS("epp", -1, 0, 1, KHZ, 192000, 228000, 300000, 396000, 492000, 516000, 552000, 552000, 600000, 600000),
- CORE_DVFS("2d", -1, 1, 1, KHZ, 240000, 324000, 420000, 492000, 528000, 564000, 600000, 636000, 672000),
- CORE_DVFS("3d", -1, 1, 1, KHZ, 240000, 324000, 420000, 492000, 528000, 564000, 600000, 636000, 672000),
- CORE_DVFS("epp", -1, 1, 1, KHZ, 240000, 324000, 420000, 492000, 528000, 564000, 600000, 636000, 672000),
+ CORE_DVFS("2d", -1, 1, 1, KHZ, 240000, 324000, 420000, 492000, 528000, 564000, 600000, 636000, 672000, 840000),
+ CORE_DVFS("3d", -1, 1, 1, KHZ, 240000, 324000, 420000, 492000, 528000, 564000, 600000, 636000, 672000, 840000),
+ CORE_DVFS("epp", -1, 1, 1, KHZ, 240000, 324000, 420000, 492000, 528000, 564000, 600000, 636000, 672000, 840000),
- CORE_DVFS("msenc", 0, 0, 1, KHZ, 144000, 182000, 240000, 312000, 384000, 408000, 408000, 408000, 408000),
- CORE_DVFS("se", 0, 0, 1, KHZ, 144000, 182000, 240000, 312000, 384000, 408000, 408000, 408000, 408000),
- CORE_DVFS("tsec", 0, 0, 1, KHZ, 144000, 182000, 240000, 312000, 384000, 408000, 408000, 408000, 408000),
- CORE_DVFS("vde", 0, 0, 1, KHZ, 144000, 182000, 240000, 312000, 384000, 408000, 408000, 408000, 408000),
+ CORE_DVFS("msenc", 0, 0, 1, KHZ, 144000, 182000, 240000, 312000, 384000, 408000, 408000, 408000, 408000, 408000),
+ CORE_DVFS("se", 0, 0, 1, KHZ, 144000, 182000, 240000, 312000, 384000, 408000, 408000, 408000, 408000, 408000),
+ CORE_DVFS("tsec", 0, 0, 1, KHZ, 144000, 182000, 240000, 312000, 384000, 408000, 408000, 408000, 408000, 408000),
+ CORE_DVFS("vde", 0, 0, 1, KHZ, 144000, 182000, 240000, 312000, 384000, 408000, 408000, 408000, 408000, 408000),
- CORE_DVFS("msenc", 0, 1, 1, KHZ, 228000, 288000, 360000, 408000, 408000, 408000, 408000, 408000, 408000),
- CORE_DVFS("se", 0, 1, 1, KHZ, 228000, 288000, 360000, 408000, 408000, 408000, 408000, 408000, 408000),
- CORE_DVFS("tsec", 0, 1, 1, KHZ, 228000, 288000, 360000, 408000, 408000, 408000, 408000, 408000, 408000),
- CORE_DVFS("vde", 0, 1, 1, KHZ, 228000, 288000, 360000, 408000, 408000, 408000, 408000, 408000, 408000),
+ CORE_DVFS("msenc", 0, 1, 1, KHZ, 228000, 288000, 360000, 408000, 408000, 408000, 408000, 408000, 408000, 408000),
+ CORE_DVFS("se", 0, 1, 1, KHZ, 228000, 288000, 360000, 408000, 408000, 408000, 408000, 408000, 408000, 408000),
+ CORE_DVFS("tsec", 0, 1, 1, KHZ, 228000, 288000, 360000, 408000, 408000, 408000, 408000, 408000, 408000, 408000),
+ CORE_DVFS("vde", 0, 1, 1, KHZ, 228000, 288000, 360000, 408000, 408000, 408000, 408000, 408000, 408000, 408000),
- CORE_DVFS("msenc", 1, 1, 1, KHZ, 228000, 288000, 360000, 420000, 468000, 480000, 480000, 480000, 480000),
- CORE_DVFS("se", 1, 1, 1, KHZ, 228000, 288000, 360000, 420000, 468000, 480000, 480000, 480000, 480000),
- CORE_DVFS("tsec", 1, 1, 1, KHZ, 228000, 288000, 360000, 420000, 468000, 480000, 480000, 480000, 480000),
- CORE_DVFS("vde", 1, 1, 1, KHZ, 228000, 288000, 360000, 420000, 468000, 480000, 480000, 480000, 480000),
+ CORE_DVFS("msenc", 1, 1, 1, KHZ, 228000, 288000, 360000, 420000, 468000, 480000, 480000, 480000, 480000, 480000),
+ CORE_DVFS("se", 1, 1, 1, KHZ, 228000, 288000, 360000, 420000, 468000, 480000, 480000, 480000, 480000, 480000),
+ CORE_DVFS("tsec", 1, 1, 1, KHZ, 228000, 288000, 360000, 420000, 468000, 480000, 480000, 480000, 480000, 480000),
+ CORE_DVFS("vde", 1, 1, 1, KHZ, 228000, 288000, 360000, 420000, 468000, 480000, 480000, 480000, 480000, 480000),
- CORE_DVFS("host1x", 0, 0, 1, KHZ, 144000, 188000, 240000, 276000, 324000, 336000, 336000, 336000, 336000),
- CORE_DVFS("host1x", 0, 1, 1, KHZ, 180000, 228000, 300000, 336000, 336000, 336000, 336000, 336000, 336000),
- CORE_DVFS("host1x", 1, 1, 1, KHZ, 180000, 228000, 300000, 336000, 372000, 384000, 384000, 384000, 384000),
+ CORE_DVFS("host1x", 0, 0, 1, KHZ, 144000, 188000, 240000, 276000, 324000, 336000, 336000, 336000, 336000, 336000),
+ CORE_DVFS("host1x", 0, 1, 1, KHZ, 180000, 228000, 300000, 336000, 336000, 336000, 336000, 336000, 336000, 336000),
+ CORE_DVFS("host1x", 1, 1, 1, KHZ, 180000, 228000, 300000, 336000, 372000, 384000, 384000, 384000, 384000, 384000),
#ifdef CONFIG_TEGRA_DUAL_CBUS
- CORE_DVFS("c2bus", -1, 0, 1, KHZ, 192000, 228000, 300000, 396000, 492000, 516000, 552000, 552000, 600000),
- CORE_DVFS("c2bus", -1, 1, 1, KHZ, 240000, 324000, 420000, 492000, 528000, 564000, 600000, 636000, 672000),
- CORE_DVFS("c3bus", 0, 0, 1, KHZ, 144000, 182000, 240000, 312000, 384000, 408000, 408000, 408000, 408000),
- CORE_DVFS("c3bus", 0, 1, 1, KHZ, 228000, 288000, 360000, 408000, 408000, 408000, 408000, 408000, 408000),
- CORE_DVFS("c3bus", 1, 1, 1, KHZ, 228000, 288000, 360000, 420000, 468000, 480000, 480000, 480000, 480000),
+ CORE_DVFS("c2bus", -1, 0, 1, KHZ, 192000, 228000, 300000, 396000, 492000, 516000, 552000, 552000, 600000, 600000),
+ CORE_DVFS("c2bus", -1, 1, 1, KHZ, 240000, 324000, 420000, 492000, 528000, 564000, 600000, 636000, 672000, 840000),
+ CORE_DVFS("c3bus", 0, 0, 1, KHZ, 144000, 182000, 240000, 312000, 384000, 408000, 408000, 408000, 408000, 408000),
+ CORE_DVFS("c3bus", 0, 1, 1, KHZ, 228000, 288000, 360000, 408000, 408000, 408000, 408000, 408000, 408000, 408000),
+ CORE_DVFS("c3bus", 1, 1, 1, KHZ, 228000, 288000, 360000, 420000, 468000, 480000, 480000, 480000, 480000, 480000),
#else
- CORE_DVFS("cbus", 0, 0, 1, KHZ, 144000, 182000, 240000, 312000, 384000, 408000, 408000, 408000, 408000),
- CORE_DVFS("cbus", 0, 1, 1, KHZ, 228000, 288000, 360000, 408000, 408000, 408000, 408000, 408000, 408000),
- CORE_DVFS("cbus", 1, 1, 1, KHZ, 228000, 288000, 360000, 420000, 468000, 480000, 480000, 480000, 480000),
+ CORE_DVFS("cbus", 0, 0, 1, KHZ, 144000, 182000, 240000, 312000, 384000, 408000, 408000, 408000, 408000, 408000),
+ CORE_DVFS("cbus", 0, 1, 1, KHZ, 228000, 288000, 360000, 408000, 408000, 408000, 408000, 408000, 408000, 408000),
+ CORE_DVFS("cbus", 1, 1, 1, KHZ, 228000, 288000, 360000, 420000, 468000, 480000, 480000, 480000, 480000, 480000),
#endif
- CORE_DVFS("pll_m", -1, -1, 1, KHZ, 800000, 800000, 1066000, 1066000, 1066000, 1066000, 1066000, 1066000, 1066000),
- CORE_DVFS("pll_c", -1, -1, 1, KHZ, 800000, 800000, 1066000, 1066000, 1066000, 1066000, 1066000, 1066000, 1066000),
- CORE_DVFS("pll_c2", -1, -1, 1, KHZ, 800000, 800000, 1066000, 1066000, 1066000, 1066000, 1066000, 1066000, 1066000),
- CORE_DVFS("pll_c3", -1, -1, 1, KHZ, 800000, 800000, 1066000, 1066000, 1066000, 1066000, 1066000, 1066000, 1066000),
+ CORE_DVFS("pll_m", -1, -1, 1, KHZ, 800000, 800000, 1066000, 1066000, 1066000, 1066000, 1066000, 1066000, 1066000, 1066000),
+ CORE_DVFS("pll_c", -1, -1, 1, KHZ, 800000, 800000, 1066000, 1066000, 1066000, 1066000, 1066000, 1066000, 1066000, 1066000),
+ CORE_DVFS("pll_c2", -1, -1, 1, KHZ, 800000, 800000, 1066000, 1066000, 1066000, 1066000, 1066000, 1066000, 1066000, 1066000),
+ CORE_DVFS("pll_c3", -1, -1, 1, KHZ, 800000, 800000, 1066000, 1066000, 1066000, 1066000, 1066000, 1066000, 1066000, 1066000),
- /* Core voltages (mV): 900, 950, 1000, 1050, 1100, 1120, 1170, 1200, 1250 */
+ /* Core voltages (mV): 900, 950, 1000, 1050, 1100, 1120, 1170, 1200, 1250, 1390 */
/* Clock limits for I/O peripherals */
- CORE_DVFS("sbc1", -1, -1, 1, KHZ, 48000, 48000, 48000, 48000, 52000, 52000, 52000, 52000, 52000),
- CORE_DVFS("sbc2", -1, -1, 1, KHZ, 48000, 48000, 48000, 48000, 52000, 52000, 52000, 52000, 52000),
- CORE_DVFS("sbc3", -1, -1, 1, KHZ, 48000, 48000, 48000, 48000, 52000, 52000, 52000, 52000, 52000),
- CORE_DVFS("sbc4", -1, -1, 1, KHZ, 48000, 48000, 48000, 48000, 52000, 52000, 52000, 52000, 52000),
- CORE_DVFS("sbc5", -1, -1, 1, KHZ, 48000, 48000, 48000, 48000, 52000, 52000, 52000, 52000, 52000),
- CORE_DVFS("sbc6", -1, -1, 1, KHZ, 48000, 48000, 48000, 48000, 52000, 52000, 52000, 52000, 52000),
+ CORE_DVFS("sbc1", -1, -1, 1, KHZ, 48000, 48000, 48000, 48000, 52000, 52000, 52000, 52000, 52000, 52000),
+ CORE_DVFS("sbc2", -1, -1, 1, KHZ, 48000, 48000, 48000, 48000, 52000, 52000, 52000, 52000, 52000, 52000),
+ CORE_DVFS("sbc3", -1, -1, 1, KHZ, 48000, 48000, 48000, 48000, 52000, 52000, 52000, 52000, 52000, 52000),
+ CORE_DVFS("sbc4", -1, -1, 1, KHZ, 48000, 48000, 48000, 48000, 52000, 52000, 52000, 52000, 52000, 52000),
+ CORE_DVFS("sbc5", -1, -1, 1, KHZ, 48000, 48000, 48000, 48000, 52000, 52000, 52000, 52000, 52000, 52000),
+ CORE_DVFS("sbc6", -1, -1, 1, KHZ, 48000, 48000, 48000, 48000, 52000, 52000, 52000, 52000, 52000, 52000),
- CORE_DVFS("sdmmc1", -1, -1, 1, KHZ, 1, 81600, 81600, 81600, 156000, 156000, 156000, 156000, 156000),
- CORE_DVFS("sdmmc3", -1, -1, 1, KHZ, 1, 81600, 81600, 81600, 156000, 156000, 156000, 156000, 156000),
- CORE_DVFS("sdmmc4", -1, -1, 1, KHZ, 102000, 102000, 102000, 102000, 156000, 156000, 156000, 156000, 156000),
+ CORE_DVFS("sdmmc1", -1, -1, 1, KHZ, 1, 81600, 81600, 81600, 156000, 156000, 156000, 156000, 156000, 156000),
+ CORE_DVFS("sdmmc3", -1, -1, 1, KHZ, 1, 81600, 81600, 81600, 156000, 156000, 156000, 156000, 156000, 156000),
+ CORE_DVFS("sdmmc4", -1, -1, 1, KHZ, 102000, 102000, 102000, 102000, 156000, 156000, 156000, 156000, 156000, 156000),
- CORE_DVFS("hdmi", -1, -1, 1, KHZ, 148500, 148500, 148500, 297000, 297000, 297000, 297000, 297000, 297000),
+ CORE_DVFS("hdmi", -1, -1, 1, KHZ, 148500, 148500, 148500, 297000, 297000, 297000, 297000, 297000, 297000, 297000),
/*
* The clock rate for the display controllers that determines the
@@ -350,16 +350,16 @@ static struct dvfs core_dvfs_table[] = {
* to the display block. Disable auto-dvfs on the display clocks,
* and let the display driver call tegra_dvfs_set_rate manually
*/
- CORE_DVFS("disp1", -1, -1, 0, KHZ, 166000, 166000, 166000, 297000, 297000, 297000, 297000, 297000, 297000),
- CORE_DVFS("disp2", -1, -1, 0, KHZ, 166000, 166000, 166000, 297000, 297000, 297000, 297000, 297000, 297000),
+ CORE_DVFS("disp1", -1, -1, 0, KHZ, 166000, 166000, 166000, 297000, 297000, 297000, 297000, 297000, 297000, 297000),
+ CORE_DVFS("disp2", -1, -1, 0, KHZ, 166000, 166000, 166000, 297000, 297000, 297000, 297000, 297000, 297000, 297000),
/* xusb clocks */
- CORE_DVFS("xusb_falcon_src", -1, -1, 1, KHZ, 1, 336000, 336000, 336000, 336000, 336000, 336000, 336000, 336000),
- CORE_DVFS("xusb_host_src", -1, -1, 1, KHZ, 1, 112000, 112000, 112000, 112000, 112000, 112000, 112000, 112000),
- CORE_DVFS("xusb_dev_src", -1, -1, 1, KHZ, 1, 58300, 58300, 112000, 112000, 112000, 112000, 112000, 112000),
- CORE_DVFS("xusb_ss_src", -1, -1, 1, KHZ, 1, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000),
- CORE_DVFS("xusb_fs_src", -1, -1, 1, KHZ, 1, 48000, 48000, 48000, 48000, 48000, 48000, 48000, 48000),
- CORE_DVFS("xusb_hs_src", -1, -1, 1, KHZ, 1, 60000, 60000, 60000, 60000, 60000, 60000, 60000, 60000),
+ CORE_DVFS("xusb_falcon_src", -1, -1, 1, KHZ, 1, 336000, 336000, 336000, 336000, 336000, 336000, 336000, 336000, 336000),
+ CORE_DVFS("xusb_host_src", -1, -1, 1, KHZ, 1, 112000, 112000, 112000, 112000, 112000, 112000, 112000, 112000, 112000),
+ CORE_DVFS("xusb_dev_src", -1, -1, 1, KHZ, 1, 58300, 58300, 112000, 112000, 112000, 112000, 112000, 112000, 112000),
+ CORE_DVFS("xusb_ss_src", -1, -1, 1, KHZ, 1, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000),
+ CORE_DVFS("xusb_fs_src", -1, -1, 1, KHZ, 1, 48000, 48000, 48000, 48000, 48000, 48000, 48000, 48000, 48000),
+ CORE_DVFS("xusb_hs_src", -1, -1, 1, KHZ, 1, 60000, 60000, 60000, 60000, 60000, 60000, 60000, 60000, 60000),
#endif
};
diff --git a/arch/arm/mach-tegra/tegra11_edp.c b/arch/arm/mach-tegra/tegra11_edp.c
index ee7b9c5fecdb..12be0426e234 100644
--- a/arch/arm/mach-tegra/tegra11_edp.c
+++ b/arch/arm/mach-tegra/tegra11_edp.c
@@ -274,8 +274,8 @@ static struct core_edp_entry core_edp_table[] = {
},
/* favor gpu */
{ /* core modules power state 0 (all ON) */
- {{ 924, 816 },
- { 924, 816 },
+ {{ 924, 840 },
+ { 924, 828 },
{ 924, 816 },
{ 924, 648 },
}
diff --git a/arch/arm/mach-tegra/tegra11_speedo.c b/arch/arm/mach-tegra/tegra11_speedo.c
index f34e65dea9a0..a1c2b9407aee 100644
--- a/arch/arm/mach-tegra/tegra11_speedo.c
+++ b/arch/arm/mach-tegra/tegra11_speedo.c
@@ -207,6 +207,8 @@ int tegra_core_speedo_mv(void)
return 1170;
/* fall thru if core_process_id = 0 */
case 1:
+ if (tegra_sku_id == 0x4)
+ return 1390;
return 1250;
default:
BUG();