diff options
| author | Alex Frid <afrid@nvidia.com> | 2010-04-12 22:03:41 -0700 |
|---|---|---|
| committer | Gary King <gking@nvidia.com> | 2010-04-14 18:11:28 -0700 |
| commit | 99c3e7688639940946f8344df4741dcfc9a47264 (patch) | |
| tree | 2cf374237316f8d82fc8d4a9b6305d6d8a5d566c /arch | |
| parent | 15dd321ef1de7508952438128b4138927c48dd25 (diff) | |
tegra ODM: Updated EMC DVFS table on Whistler.
Updated EMC DVFS table on Whistler:
- made sure RFC settings are above 5 for all entries
- disabled DQS_PULLD for 150MHz entry and below
- lowered operational voltage for 18MHz and 27MHz entries from 1.0V to 0.95V
Change-Id: I682ed68bb5bfd4497a214065007159ab2fe042b7
Reviewed-on: http://git-master/r/1089
Reviewed-by: Sharad Ranjan <shranjan@nvidia.com>
Tested-by: Sharad Ranjan <shranjan@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
Diffstat (limited to 'arch')
| -rwxr-xr-x | arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query.c b/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query.c index fa8098570209..a66b46ae3323 100755 --- a/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query.c +++ b/arch/arm/mach-tegra/odm_kit/query/whistler/nvodm_query.c @@ -238,11 +238,11 @@ static const NvOdmSdramControllerConfigAdv s_NvOdmE1108HynixEmcConfigTable[] = { 0x20, /* Rev 2.0 */ 18000, /* SDRAM frquency */ - 1000, /* EMC core voltage */ + 950, /* EMC core voltage */ 46, /* Number of EMC parameters below */ { 0x00000002, /* RC */ - 0x00000003, /* RFC */ + 0x00000006, /* RFC */ 0x00000003, /* RAS */ 0x00000003, /* RP */ 0x00000006, /* R2W */ @@ -277,7 +277,7 @@ static const NvOdmSdramControllerConfigAdv s_NvOdmE1108HynixEmcConfigTable[] = 0x00000003, /* FBIO_CFG6 */ 0x00000000, /* ODT_WRITE */ 0x00000000, /* ODT_READ */ - 0x00000282, /* FBIO_CFG5 */ + 0x00000082, /* FBIO_CFG5 */ 0x00780006, /* CFG_DIG_DLL */ 0x00000010, /* DLL_XFORM_DQS */ 0x00000008, /* DLL_XFORM_QUSE */ @@ -292,11 +292,11 @@ static const NvOdmSdramControllerConfigAdv s_NvOdmE1108HynixEmcConfigTable[] = { 0x20, /* Rev 2.0 */ 27000, /* SDRAM frquency */ - 1000, /* EMC core voltage */ + 950, /* EMC core voltage */ 46, /* Number of EMC parameters below */ { 0x00000002, /* RC */ - 0x00000004, /* RFC */ + 0x00000006, /* RFC */ 0x00000003, /* RAS */ 0x00000003, /* RP */ 0x00000006, /* R2W */ @@ -331,7 +331,7 @@ static const NvOdmSdramControllerConfigAdv s_NvOdmE1108HynixEmcConfigTable[] = 0x00000003, /* FBIO_CFG6 */ 0x00000000, /* ODT_WRITE */ 0x00000000, /* ODT_READ */ - 0x00000282, /* FBIO_CFG5 */ + 0x00000082, /* FBIO_CFG5 */ 0x00780006, /* CFG_DIG_DLL */ 0x00000010, /* DLL_XFORM_DQS */ 0x00000008, /* DLL_XFORM_QUSE */ @@ -385,7 +385,7 @@ static const NvOdmSdramControllerConfigAdv s_NvOdmE1108HynixEmcConfigTable[] = 0x00000000, /* FBIO_CFG6 */ 0x00000000, /* ODT_WRITE */ 0x00000000, /* ODT_READ */ - 0x00000282, /* FBIO_CFG5 */ + 0x00000082, /* FBIO_CFG5 */ 0x00780006, /* CFG_DIG_DLL */ 0x00000010, /* DLL_XFORM_DQS */ 0x00000008, /* DLL_XFORM_QUSE */ @@ -439,7 +439,7 @@ static const NvOdmSdramControllerConfigAdv s_NvOdmE1108HynixEmcConfigTable[] = 0x00000000, /* FBIO_CFG6 */ 0x00000000, /* ODT_WRITE */ 0x00000000, /* ODT_READ */ - 0x00000282, /* FBIO_CFG5 */ + 0x00000082, /* FBIO_CFG5 */ 0xD0780323, /* CFG_DIG_DLL */ 0x007FD010, /* DLL_XFORM_DQS */ 0x00000010, /* DLL_XFORM_QUSE */ @@ -493,7 +493,7 @@ static const NvOdmSdramControllerConfigAdv s_NvOdmE1108HynixEmcConfigTable[] = 0x00000001, /* FBIO_CFG6 */ 0x00000000, /* ODT_WRITE */ 0x00000000, /* ODT_READ */ - 0x00000282, /* FBIO_CFG5 */ + 0x00000082, /* FBIO_CFG5 */ 0xD05E0323, /* CFG_DIG_DLL */ 0x007FD010, /* DLL_XFORM_DQS */ 0x00000010, /* DLL_XFORM_QUSE */ |