ARM: tegra: power: Add read fences in power gating

To assure post of the previous writes through Tegra interconnect
added read fences in the following power gating code paths:

- Seconadry CPU boot ungating (path taken on Tegra11)
- MC client ungating flush done (path taken on all platforms)

Bug 1484343

Change-Id: Ie09ef37135beae0ed0beb1cd4d7e96187ba9be26
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/385403
(cherry picked from commit 28b107dcb3aa122de8e94e48af548140d519298f)
Reviewed-on: http://git-master/r/396764
Reviewed-by: Min-wuk Lee <mlee@nvidia.com>
Tested-by: Min-wuk Lee <mlee@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Harry Hong <hhong@nvidia.com>

4 files changed, 7 insertions, 4 deletions

diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 480e8d051488..a62ceaa5805d 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -7,7 +7,7 @@
  *  Copyright (C) 2009 Palm
  *  All Rights Reserved
  *
- *  Copyright (C) 2010-2013 NVIDIA Corporation
+ *  Copyright (C) 2010-2014 NVIDIA Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -279,6 +279,7 @@ static int tegra11x_power_up_cpu(unsigned int cpu)
 
 		reg = PMC_TOGGLE_START | TEGRA_CPU_POWERGATE_ID(cpu);
 		pmc_writel(reg, PWRGATE_TOGGLE);
+		pmc_readl(PWRGATE_TOGGLE);
 	}
 
 	return 0;
diff --git a/arch/arm/mach-tegra/powergate-t11x.c b/arch/arm/mach-tegra/powergate-t11x.c
index 55485804542d..5b0838593d09 100644
--- a/arch/arm/mach-tegra/powergate-t11x.c
+++ b/arch/arm/mach-tegra/powergate-t11x.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2012-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -458,6 +458,7 @@ int tegra11x_powergate_mc_flush_done(int id)
 		rst_ctrl = mc_read(MC_CLIENT_HOTRESET_CTRL);
 		rst_ctrl &= ~(1 << mcClientBit);
 		mc_write(rst_ctrl, MC_CLIENT_HOTRESET_CTRL);
+		mc_read(MC_CLIENT_HOTRESET_CTRL);
 
 		spin_unlock_irqrestore(&tegra11x_powergate_lock, flags);
 	}
diff --git a/arch/arm/mach-tegra/powergate-t30.c b/arch/arm/mach-tegra/powergate-t30.c
index a645f364ab69..cecaeba6aeda 100644
--- a/arch/arm/mach-tegra/powergate-t30.c
+++ b/arch/arm/mach-tegra/powergate-t30.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2012-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -309,7 +309,7 @@ int tegra3_powergate_mc_flush_done(int id)
 		rst_ctrl = mc_read(MC_CLIENT_HOTRESET_CTRL);
 		rst_ctrl &= ~(1 << mcClientBit);
 		mc_write(rst_ctrl, MC_CLIENT_HOTRESET_CTRL);
-
+		mc_read(MC_CLIENT_HOTRESET_CTRL);
 		spin_unlock_irqrestore(&tegra3_powergate_lock, flags);
 	}
 
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index 771fe604b2fe..f6dbd29feef4 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -80,6 +80,7 @@ int tegra_powergate_set(int id, bool new_state)
 		/* CPU ungated in s/w only during boot/resume with outer
 		   waiting loop and no contention from other CPUs */
 		pmc_write(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
+		pmc_read(PWRGATE_TOGGLE);
 		spin_unlock_irqrestore(lock, flags);
 		return 0;
 	}