diff options
| author | Anson Huang <b20788@freescale.com> | 2015-04-07 18:20:28 +0800 |
|---|---|---|
| committer | Jason Liu <r64343@freescale.com> | 2015-05-08 17:24:17 +0800 |
| commit | 00a16717aafea4a3cad20c7cf65ae5f4dde26224 (patch) | |
| tree | 9bda4ff127da1df90387b2eb36c4d4e7c799b017 /arch | |
| parent | 04e28facd044a5da24ca248a36018c3638eda216 (diff) | |
MLK-10595-1 ARM: imx: correct gpc a7_bsc wakeup source setting
GPC_LPCR_A7_BSC should be set to be waked up by GIC/GPC both,
the value should be 0x3, otherwise, first time DSM will be
entered by mistake when program the GPC low power mode register
but ARM NOT enter wfi yet.
Signed-off-by: Anson Huang <b20788@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-imx/gpcv2.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/gpcv2.c b/arch/arm/mach-imx/gpcv2.c index 198e0638bbd9..7c4691eed110 100644 --- a/arch/arm/mach-imx/gpcv2.c +++ b/arch/arm/mach-imx/gpcv2.c @@ -512,7 +512,7 @@ void __init imx_gpcv2_init(void) } /* only external IRQs to wake up LPM and core 0/1 */ - writel_relaxed(BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP, + writel_relaxed(0x3 << BP_LPCR_A7_BSC_IRQ_SRC, gpc_base + GPC_LPCR_A7_BSC); /* mask m4 dsm trigger */ writel_relaxed(readl_relaxed(gpc_base + GPC_LPCR_M4) | |