MLK-10615: ARM: imx7d: uart: set clock parents from dts

* Use devicetree clock bindings to set clock parent for UARTx_ROOT_CLKs
* Remove fixed configuration from MSL clk-imx7ds.c to be able to override
  settings via dts.

Signed-off-by: Adrian Alonso <aalonso@freescale.com>

4 files changed, 14 insertions, 8 deletions

diff --git a/arch/arm/boot/dts/imx7d-12x12-arm2.dts b/arch/arm/boot/dts/imx7d-12x12-arm2.dts
index f9ce88331e9c..1e15e91f71ca 100644
--- a/arch/arm/boot/dts/imx7d-12x12-arm2.dts
+++ b/arch/arm/boot/dts/imx7d-12x12-arm2.dts
@@ -338,6 +338,8 @@
 &uart1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart1_1>;
+	assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
+	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 	status = "okay";
 };
 
@@ -345,6 +347,8 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart3_1>;
 	fsl,uart-has-rtscts;
+	assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
+	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 	status = "okay";
 	/* for DTE mode, add below change */
 	/* fsl,dte-mode;*/
diff --git a/arch/arm/boot/dts/imx7d-19x19-arm2.dts b/arch/arm/boot/dts/imx7d-19x19-arm2.dts
index 4c3ccfea76c9..2442024263a8 100644
--- a/arch/arm/boot/dts/imx7d-19x19-arm2.dts
+++ b/arch/arm/boot/dts/imx7d-19x19-arm2.dts
@@ -217,6 +217,8 @@
 &uart1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart1_1>;
+	assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
+	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 	status = "okay";
 };
 
@@ -224,6 +226,8 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart3_1>;
 	fsl,uart-has-rtscts;
+	assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
+	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 	status = "okay";
 	/* for DTE mode, add below change */
 	/* fsl,dte-mode;*/
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index 927032cb0f6e..261da36ed61e 100644
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -844,12 +844,16 @@
 &uart1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart1>;
+	assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
+	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 	status = "okay";
 };
 
 &uart5 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart5>;
+	assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
+	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 	fsl,uart-has-rtscts;
 	status = "okay";
 };
@@ -857,6 +861,8 @@
 &uart6 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart6>;
+	assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>;
+	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 	fsl,uart-has-rtscts;
 	status = "okay";
 };
diff --git a/arch/arm/mach-imx/clk-imx7d.c b/arch/arm/mach-imx/clk-imx7d.c
index 1282a8928006..0f7f6928757a 100644
--- a/arch/arm/mach-imx/clk-imx7d.c
+++ b/arch/arm/mach-imx/clk-imx7d.c
@@ -905,14 +905,6 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
 	/* set uart module clock's parent clock source that must be great then 80Mhz */
 	if (uart_from_osc)
 		imx_clk_set_parent(clks[IMX7D_UART1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);
-	else
-		imx_clk_set_parent(clks[IMX7D_UART1_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]);
-	imx_clk_set_parent(clks[IMX7D_UART2_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]);
-	imx_clk_set_parent(clks[IMX7D_UART3_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]);
-	imx_clk_set_parent(clks[IMX7D_UART4_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]);
-	imx_clk_set_parent(clks[IMX7D_UART5_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]);
-	imx_clk_set_parent(clks[IMX7D_UART6_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]);
-	imx_clk_set_parent(clks[IMX7D_UART7_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]);
 
 	/* set pcie root's parent clk source */
 	imx_clk_set_parent(clks[IMX7D_PCIE_CTRL_ROOT_SRC], clks[IMX7D_PLL_ENET_MAIN_250M_CLK]);