diff options
| author | Liu Ying <Ying.Liu@freescale.com> | 2015-04-30 14:59:41 +0800 |
|---|---|---|
| committer | Jason Liu <r64343@freescale.com> | 2015-05-08 17:25:15 +0800 |
| commit | 746632a180778191dba738774d62fea292f937ff (patch) | |
| tree | 05fd25813f4430a8c60cee55cd451adf1483b71b /arch | |
| parent | 67edcd0c6f723e74db83a20bca728ad4f10ed586 (diff) | |
MLK-10747 ARM: clk-imx6q: Set LDB_DI_SEL parent to be PLL2_PFD0_352M for i.MX6QP
This patch sets LDB_DI[0/1]_SEL clock parent to be PLL2_PFD0_352M
clock for i.MX6QP so that we may get correct 65MHz pixel clock rate
for Hannstar LVDS panel.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit c163cfce94d6a07dea18703407a4068648424a46)
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-imx/clk-imx6q.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 0d7ad008e41c..e6d82a2fcf63 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -566,6 +566,11 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk_register_clkdev(clk[IMX6QDL_CLK_GPT_3M], "gpt_3m", "imx-gpt.0"); clk_register_clkdev(clk[IMX6QDL_CLK_ENET_REF], "enet_ref", NULL); + if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0) { + imx_clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL2_PFD0_352M]); + imx_clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL2_PFD0_352M]); + } + /* ipu clock initialization */ imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); |