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authorLuwei Zhou <b45643@freescale.com>2015-04-08 14:52:56 +0800
committerJason Liu <r64343@freescale.com>2015-05-08 17:24:30 +0800
commitd98d921d9d5f0610a416a10162ce1f922d8331d4 (patch)
tree6c2251e989788b2d1bbd4aa7848b798511d155fb /arch
parente334bb2f448d06963a6ce1ecfc12b9b50ba556c9 (diff)
MLK-10600-3 ARM: clk_imx7d: Select IMX7D_PLL_SYS_MAIN_120M_CLK as the parent of IMX7D_SIM1_ROOT_SRC.
Select IMX7D_PLL_SYS_MAIN_120M_CLK as the parent of IMX7D_SIM1_ROOT_SRC. Signed-off-by: Luwei Zhou <b45643@freescale.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-imx/clk-imx7d.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/clk-imx7d.c b/arch/arm/mach-imx/clk-imx7d.c
index be4edbfbd4a8..1282a8928006 100644
--- a/arch/arm/mach-imx/clk-imx7d.c
+++ b/arch/arm/mach-imx/clk-imx7d.c
@@ -928,6 +928,9 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
/* set lcdif pixel root clock source to get the required 33Mhz clock */
imx_clk_set_parent(clks[IMX7D_LCDIF_PIXEL_ROOT_SRC], clks[IMX7D_PLL_VIDEO_POST_DIV]);
+ /* set parent of SIM1 root clock */
+ imx_clk_set_parent(clks[IMX7D_SIM1_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_120M_CLK]);
+
mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx7d-gpt"));
}
CLK_OF_DECLARE(imx7d, "fsl,imx7d-ccm", imx7d_clocks_init);