diff options
| author | Zhang Jiejing <jiejing.zhang@freescale.com> | 2012-12-11 15:34:25 +0800 |
|---|---|---|
| committer | Tapani <tapani@vmail.me> | 2013-03-29 11:41:11 +0800 |
| commit | 98d86b993c7259b9203f904d9ab71ea704fb0e6a (patch) | |
| tree | 435382a984265ab5f016d485170392c218ae831a /arch | |
| parent | 5393d4e48bbf63039a118da73079284e1a825f0a (diff) | |
ENGR00235817 mx6: use SNVS LPGPR register to store boot mode value.
After using POR reset, the content in SRC will be reset.
See RM: 63.5.1.2.3 IPP_RESET_B(POR)
Because POR reset will reset most of register in IC, so use
SNVS_LP General Purpose Register (LPGPR) to store the boot mode value.
Below copy from SNVS_BlockGuide.pdf:
The SNVS_LP General Purpose Register provides a 32 bit read write
register, which can be used by any application for retaining 32 bit
data during a power-down mode
This Patch will use [7,8] bits of this register.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-mx6/system.c | 10 | ||||
| -rw-r--r-- | arch/arm/plat-mxc/include/mach/mx6.h | 2 |
2 files changed, 7 insertions, 5 deletions
diff --git a/arch/arm/mach-mx6/system.c b/arch/arm/mach-mx6/system.c index 6ecd51e9f9ea..d962956d312e 100644 --- a/arch/arm/mach-mx6/system.c +++ b/arch/arm/mach-mx6/system.c @@ -563,7 +563,7 @@ void mxc_clear_mfgmode(void) #endif #ifdef CONFIG_MXC_REBOOT_ANDROID_CMD -/* This function will set a bit on SRC_GPR10[7-8] bits to enter +/* This function will set a bit on SNVS_LPGPR[7-8] bits to enter * special boot mode. These bits will not clear by watchdog reset, so * it can be checked by bootloader to choose enter different mode.*/ @@ -574,18 +574,18 @@ void do_switch_recovery(void) { u32 reg; - reg = __raw_readl(SRC_BASE_ADDR + SRC_GPR10); + reg = __raw_readl(MX6Q_SNVS_BASE_ADDR + SNVS_LPGPR); reg |= ANDROID_RECOVERY_BOOT; - __raw_writel(reg, SRC_BASE_ADDR + SRC_GPR10); + __raw_writel(reg, MX6Q_SNVS_BASE_ADDR + SNVS_LPGPR); } void do_switch_fastboot(void) { u32 reg; - reg = __raw_readl(SRC_BASE_ADDR + SRC_GPR10); + reg = __raw_readl(MX6Q_SNVS_BASE_ADDR + SNVS_LPGPR); reg |= ANDROID_FASTBOOT_BOOT; - __raw_writel(reg, SRC_BASE_ADDR + SRC_GPR10); + __raw_writel(reg, MX6Q_SNVS_BASE_ADDR + SNVS_LPGPR); } #endif diff --git a/arch/arm/plat-mxc/include/mach/mx6.h b/arch/arm/plat-mxc/include/mach/mx6.h index 48b04b104560..bb22de06a45a 100644 --- a/arch/arm/plat-mxc/include/mach/mx6.h +++ b/arch/arm/plat-mxc/include/mach/mx6.h @@ -302,6 +302,8 @@ #define SRC_GPR9 0x40 #define SRC_GPR10 0x44 +#define SNVS_LPGPR 0x68 + /* GPC offsets */ #define MXC_GPC_CNTR_OFFSET 0x0 |