diff options
| author | Bintian Wang <bintian.wang@huawei.com> | 2015-05-29 10:08:38 +0800 |
|---|---|---|
| committer | Michael Turquette <mturquette@linaro.org> | 2015-06-03 15:12:25 -0700 |
| commit | 72ea48610d43c59507d9ad39083d40085400ba12 (patch) | |
| tree | 826b1a5073246280adf5d90dbbecf492848af009 /drivers/clk/hisilicon/clk.h | |
| parent | 2a40a2ea109269def06f991f771c2bf2f6c0f396 (diff) | |
clk: hi6220: Clock driver support for Hisilicon hi6220 SoC
Add clock drivers for hi6220 SoC, this driver controls the SoC
registers to supply different clocks to different IPs in the SoC.
We add one divider clock for hi6220 because the divider in hi6220
also has a mask bit but it doesnot obey the rule defined by flag
"CLK_DIVIDER_HIWORD_MASK", we can not get index of the mask bit by
left shift fixed bits (e.g. 16 bits), so we add this divider clock
to handle it.
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: Bintian Wang <bintian.wang@huawei.com>
Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Reviewed-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Tested-by: Will Deacon <will.deacon@arm.com>
Tested-by: Tyler Baker <tyler.baker@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk/hisilicon/clk.h')
| -rw-r--r-- | drivers/clk/hisilicon/clk.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/drivers/clk/hisilicon/clk.h b/drivers/clk/hisilicon/clk.h index 6b6f99448e01..21b403b3423a 100644 --- a/drivers/clk/hisilicon/clk.h +++ b/drivers/clk/hisilicon/clk.h @@ -79,6 +79,18 @@ struct hisi_divider_clock { const char *alias; }; +struct hi6220_divider_clock { + unsigned int id; + const char *name; + const char *parent_name; + unsigned long flags; + unsigned long offset; + u8 shift; + u8 width; + u32 mask_bit; + const char *alias; +}; + struct hisi_gate_clock { unsigned int id; const char *name; @@ -94,6 +106,9 @@ struct clk *hisi_register_clkgate_sep(struct device *, const char *, const char *, unsigned long, void __iomem *, u8, u8, spinlock_t *); +struct clk *hi6220_register_clkdiv(struct device *dev, const char *name, + const char *parent_name, unsigned long flags, void __iomem *reg, + u8 shift, u8 width, u32 mask_bit, spinlock_t *lock); struct hisi_clock_data *hisi_clk_init(struct device_node *, int); void hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *, @@ -108,4 +123,6 @@ void hisi_clk_register_gate(struct hisi_gate_clock *, int, struct hisi_clock_data *); void hisi_clk_register_gate_sep(struct hisi_gate_clock *, int, struct hisi_clock_data *); +void hi6220_clk_register_divider(struct hi6220_divider_clock *, + int, struct hisi_clock_data *); #endif /* __HISI_CLK_H */ |