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authorStefan Richter <stefanr@s5r6.in-berlin.de>2010-06-12 20:26:51 +0200
committerStefan Richter <stefanr@s5r6.in-berlin.de>2010-06-19 13:01:40 +0200
commit65b2742ac002f554f6ca0c2eab84cc62400eafdf (patch)
treea13b0dc0883a5e126f2577f8061705c4c38debc0 /drivers/firewire/core-transaction.c
parentc374ab424249b6ab91b1aee7460419d3f2c321df (diff)
firewire: 'add CSR_... support' addendum
Add a comment on which of the conflicting NODE_IDS specifications we implement. Reduce a comment on rather irrelevant register bits that can all be looked up in the spec (or from now on in the code history). Directly include the required indirectly included bug.h. Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
Diffstat (limited to 'drivers/firewire/core-transaction.c')
-rw-r--r--drivers/firewire/core-transaction.c27
1 files changed, 6 insertions, 21 deletions
diff --git a/drivers/firewire/core-transaction.c b/drivers/firewire/core-transaction.c
index 85a54da243e2..5069cfc75b50 100644
--- a/drivers/firewire/core-transaction.c
+++ b/drivers/firewire/core-transaction.c
@@ -984,29 +984,10 @@ static const struct fw_address_region registers_region =
static u32 read_state_register(struct fw_card *card)
{
- /*
- * Fixed bits (IEEE 1394-2008 8.3.2.2.1):
- * Bits 0-1 (state) always read 00=running.
- * Bits 2,3 (off, atn) are not implemented as per the spec.
- * Bit 4 (elog) is not implemented because there is no error log.
- * Bit 6 (dreq) cannot be set. It is intended to "disable requests
- * from unreliable nodes"; however, IEEE 1212 states that devices
- * may "clear their own dreq bit when it has been improperly set".
- * Our implementation might be seen as an improperly extensive
- * interpretation of "improperly", but the 1212-2001 revision
- * dropped this bit altogether, so we're in the clear. :o)
- * Bit 7 (lost) always reads 0 because a power reset has never occurred
- * during normal operation.
- * Bit 9 (linkoff) is not implemented because the PC is not powered
- * from the FireWire cable.
- * Bit 15 (gone) always reads 0. It must be set at a power/command/bus
- * reset, but then cleared when the units are ready again, which
- * happens immediately for us.
- */
- u32 value = 0x0000;
+ u32 value;
/* Bit 8 (cmstr): */
- value |= card->driver->read_csr_reg(card, CSR_STATE_CLEAR);
+ value = card->driver->read_csr_reg(card, CSR_STATE_CLEAR);
/* Bit 10 (abdicate): */
if (card->csr_abdicate)
@@ -1066,6 +1047,10 @@ static void handle_registers(struct fw_card *card, struct fw_request *request,
break;
case CSR_NODE_IDS:
+ /*
+ * per IEEE 1394-2008 8.3.22.3, not IEEE 1394.1-2004 3.2.8
+ * and 9.6, but interoperable with IEEE 1394.1-2004 bridges
+ */
if (tcode == TCODE_READ_QUADLET_REQUEST)
*data = cpu_to_be32(card->driver->
read_csr_reg(card, CSR_NODE_IDS));