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authorChaitanya Bandi <bandik@nvidia.com>2011-09-19 16:45:28 +0530
committerDan Willemsen <dwillemsen@nvidia.com>2011-11-30 21:49:43 -0800
commit276911c2ce3d7612c787786608a26ce9842aa2d8 (patch)
treec98540390e2d2010a89649fc9ac8a6c43eefaf0e /drivers/gpio
parent4add2bff97dc1be9137dd43e95fd295997aa7213 (diff)
ARM: tegra: gpio: Set a gpio to tristate or normal
Create mapping from gpio to pingroup and set gpio to normal or tristate Bug 866633 Reviewed-on: http://git-master/r/56557 (cherry picked from commit 321ded98d41170b9e32d60177c6808492ccdf115) Change-Id: I3d1b979717f1c6b208af3df0a7dfe603e5272d21 Reviewed-on: http://git-master/r/61120 Tested-by: Bandi Krishna Chaitanya <bandik@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Rebase-Id: R5991c2cbc11aa35345fde7f08c0bfeb306e85e1e
Diffstat (limited to 'drivers/gpio')
-rw-r--r--drivers/gpio/gpio-tegra.c11
1 files changed, 8 insertions, 3 deletions
diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index 88024dd297ef..0ace5919becc 100644
--- a/drivers/gpio/gpio-tegra.c
+++ b/drivers/gpio/gpio-tegra.c
@@ -32,8 +32,8 @@
#include <asm/mach/irq.h>
#include <mach/iomap.h>
-
#include "pm-irq.h"
+#include <mach/pinmux.h>
#define GPIO_BANK(x) ((x) >> 5)
#define GPIO_PORT(x) (((x) >> 3) & 0x3)
@@ -92,7 +92,6 @@ struct tegra_gpio_bank {
#endif
};
-
static struct tegra_gpio_bank tegra_gpio_banks[] = {
{.bank = 0, .irq = INT_GPIO1},
{.bank = 1, .irq = INT_GPIO2},
@@ -111,6 +110,12 @@ static int tegra_gpio_compose(int bank, int port, int bit)
return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
}
+void tegra_gpio_set_tristate(int gpio_nr, enum tegra_tristate ts)
+{
+ int pin_group = tegra_pinmux_get_pingroup(gpio_nr);
+ tegra_pinmux_set_tristate(pin_group, ts);
+}
+
static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
{
u32 val;
@@ -149,7 +154,7 @@ static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
{
- if (( __raw_readl(GPIO_OE(offset)) >> GPIO_BIT(offset)) & 0x1)
+ if ((__raw_readl(GPIO_OE(offset)) >> GPIO_BIT(offset)) & 0x1)
return (__raw_readl(GPIO_OUT(offset)) >> GPIO_BIT(offset)) & 0x1;
return (__raw_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
}