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authorJosip Pavic <Josip.Pavic@amd.com>2019-02-05 19:27:38 -0500
committerAlex Deucher <alexander.deucher@amd.com>2019-03-05 15:09:33 -0500
commit8628d02f60d4a568d02fc12a26273a55f7718ec0 (patch)
treefb524f542175363f3142b27c8e83875e901050fc /drivers/gpu/drm/amd/display/dc/dc_dp_types.h
parent33e0a44583281a9951117e62260532e5e0ba166d (diff)
drm/amd/display: optionally optimize edp link rate based on timing
[Why] eDP v1.4 allows panels to report link rates other than RBR/HBR/HBR2, that may be more optimal for the panel's timing. Power can be saved by using a link rate closer to the required bandwidth of the panel's timing. [How] Scan the table of reported link rates from the panel, and select the minimum link rate that satisfies the bandwidth requirements of the panel's timing. Include a flag to make the feature optional. Signed-off-by: Josip Pavic <Josip.Pavic@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dc_dp_types.h')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dc_dp_types.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
index d4eab33c453b..ec403cd8b834 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
@@ -94,6 +94,8 @@ struct dc_link_settings {
enum dc_lane_count lane_count;
enum dc_link_rate link_rate;
enum dc_link_spread link_spread;
+ bool use_link_rate_set;
+ uint8_t link_rate_set;
};
struct dc_lane_settings {