diff options
| author | Ilya Bakoulin <Ilya.Bakoulin@amd.com> | 2019-03-28 14:43:29 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-06-22 09:34:09 -0500 |
| commit | 8e27a2d4cd76095c80dbbf63548175659d4b9d76 (patch) | |
| tree | d7ef5c0d536ba6ed87877d95775da7cdda2147dd /drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | |
| parent | 0213541d4b6b241a83611dd8324af024f87b5368 (diff) | |
drm/amd/display: Fix DCFCLK and SOCCLK not set
[Why]
If voltage level > 0, DCFCLK and SOCCLK could be 0 during DML
calculations, which ended up causing an assert.
[How]
Initialize dcfclk_mhz and socclk_mhz values according to the
voltage level.
Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c index aa04df64522f..dc3aa7debad5 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c @@ -2136,6 +2136,10 @@ bool dcn20_validate_bandwidth(struct dc *dc, if (pipe_cnt != pipe_idx) pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, &context->res_ctx, pipes); + pipes[0].clks_cfg.voltage = vlevel; + pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz; + pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; + /* only pipe 0 is read for voltage and dcf/soc clocks */ if (vlevel < 1) { pipes[0].clks_cfg.voltage = 1; |